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1、IC制造流程简介,1,IC制造流程简介1,基本概念,半导体是指导电能力介于导体和绝缘体之间的材料，其指四价硅中添加三价或五价化学元素而形成的电子元件，它有方向性，可以用来制造逻辑线路使电路具有处理资讯的功能。半导体的传导率可由搀杂物的浓度来控制：搀杂物的浓度越高，半导体的电阻系数就越低。P型半导体中的多数载体是电洞。硼是P型的掺杂物。N型半导体的多数载体是电子。磷，砷，锑是N型的搀杂物。集成电路（IC) 是指把特定电路所需的各种电子元件及线路缩小并制作在大小仅及2平方公分或更小的面积上的一种电子产品。集成电路主要种类有两种：逻辑LOGIC及记忆体MEMORY。前者主要执行逻辑的运算如电脑的微处
2、理器后者则如只读器READ ONLY 及随机处理器RANDOM ACCESS MEMORY等。,2,基本概念半导体是指导电能力介于导体和绝缘体之间的材料，其指四,集成电路(IC)产业主要分为设计生产测试 封装四个阶段.集成电路的生产主要分三个阶段：,基本概念,3,集成电路(IC)产业主要分为设计生产测试 封装四个阶段,4,4,基本制程,5,基本制程Wafer StartCMPOxidationWaf,基本制程,6,基本制程6,原理：在晶片表面上覆上一層感光材料，來自光源的平行光透過光罩的圖形，使得晶片表面的感光材料進行選擇性的感光。感光材料：正片經過顯影(Development)，材料所獲得的
3、圖案與光罩上相同稱為正片。負片如果彼此成互補的關係稱負片,7,原理：在晶片表面上覆上一層感光材料，來自光源的平行光透過光,微影制程 -1,8,微影制程 -1WaferWafer暴光系统暴光Wafer光刻,微影制程 -2,9,接上一页WaferWaferWafer光刻胶显影刻蚀氧化层去,掺杂物(Doping)概念:To get the extrinsic semiconductor by adding donors or acceptors, which may cause the impurity energy level. The action that adding particular
4、impurities into the semiconductor is called “doping” and the impurity that added is called the “dopant”.,Doping介绍,Doping 方法: 1. 扩散（Diffusion） 2. 离子植入（Implantation）,10,掺杂物(Doping)概念:Doping介绍Doping 方,Pre-deposition: 将掺杂物置于wafer表面.Generally used dopant resource furnace design:,Carrier gas,Heater,石英管,So
5、lid dopant source furnace,O2,Liquid dopant source,Carrier gas,Gas dopant source,Valve,O2,(a),(c),(b),扩散制程（DIFF) -1,Solid dopant source,11,Pre-deposition: 将掺杂物置于wafer表面.,Drive-in: To implant the dopant into the wafer by the thermal process,扩散制程（DIFF) -2,12,Drive-in: To implant the dopan,1. The defini
6、tion: A manufacturing process that can uniformly implants the ions into the wafer in the specified depth and consistence by selecting and accelerating ions. 2. The purpose: To change the resistance value of the semiconductor by implanting the dopant.3. Energy range (8 years ago)(1) General process：1
7、0 KeV - 180 KeV (0.35m) (100KeV for 0.18 m now)(2) Advanced process：10 KeV - 3 MeV (0.5m)(3) R&D process：0.2 KeV - 5 KeV,离子植入制程(IMP) -1,13,1. The definition:离子植入制程(IMP),DopantSource,Ion Source,MassAnalysis,Accelerator,Scanner,ElectronShower,Extractor,Farady Cap,离子植入制程(IMP) -2,14,DopantIon SourceMass
8、Accelerato,Parameters Doping elementsselection Scanning uniformity control Temperature control Concentration control,Factors The selection of the ion resource The design of the mass analyzer Scanning system Vacuum control Precise wafer position control Preciseand stable electric power supplier The m
9、easurement of the ion current (Farady Cup),DOPING参数,15,ParametersFactorsDOPING参数15,DC,Metal Target,Gas In,To The Vacuum Pump,Wafer,Plate,Collimator,PVD制程,16,DCMetal TargetGas InTo The Vac,(a) Reagents diffuse through the interface boundary layer(b) Adsorbed onto the wafer surface(c) Deposition react
10、ion happens(d) Byproducts diffuse through the interface boundary layer(e) Reagents & byproducts pass away,Heat Source,(a) (d) (b) (c),(e),Reaction,Main Stream InterfaceBoundary LayerWafer surface,Vacuum System,CVD制程,17,(a) Reagents diffuse through,(1) Thermal Oxidation The growth temperature is abov
11、e 900 0C. High quality SiO2. (2) Low Pressure CVD (LPCVD) The growth temperature is around 400 0C to 750 0C. Better step coverage ability. (3) Plasma Enhanced CVD (PECVD) The growth temperature is under 400 0C. In the case of the Al deposition and non-thermal process.,Solutions to Deposition,18,(1)
12、Thermal OxidationSolutions,Down Force,wafer,Wafer Carrier,Carrier Film,Slurry,Carrier,Wafer,Interconnects,CompositePad,Table,Polishing Pad,Polishing table,p,CMP System Schematic,Carrier Film,c,19,Down ForcewaferWafer CarrierCa,Major Parameters In CMP,SiO2 CMP: Down Force Rotating Speed (p) Type of T
13、he PadMetal and Si CMP: pH Measurement,* The lower the force-speed ratio the better the planarity,20,Major Parameters In CMPSiO2 CM,Slurry,Particle (0.1 2.0 um) Silica (Colloidal) Alumina (Dispersed)Liquor (Contains some oxidant and organic reagents in the case of metal CMP) KOH NH4OH,21,SlurryParti
14、cle 21,Wafer Cleaning,Purpose: To remove the remainsand impuriti杂质,Methods: Brush Cleaning Spray Cleaning Ultrasonic 超声波Cleaning,22,Wafer CleaningPurpose: Methods,Photo resist,SiO2,Si Substrate,PhotoMask,Positive积极 Resist,Negative负值 Resist,Etching Intro - 1,Next Page,23,Photo resistSiO2Si SubstrateP
15、h,Positive Resist,Negative Resist,Etching Intro - 2,Continue,24,Positive ResistNegative Resist,Etching Methods,Wet Etching (Isotropic) Relatively simple process High throughput Low quality Dry Etching (Anisotropic) High quality (due to the excellent pattern transfer ability) Worse selectivity,25,Etc
16、hing Methods Wet Etching (I,Wet Etching,Substrate,Thin Film,Solution,Boundary Layer,Reagent,Resultant,Reaction,Photo Resist,26,Wet EtchingSubstrateThin FilmS,(a) Isotropic Etching：A=0 (Erh=Erv),(b) Anisotropic Etching：A=1 (Erh=0),Isotropic & Anisotropic,Isotropic,27,(a) Isotropic Etching：A=0 (Erh,Qu
17、artzdome,Siliconwafer,Silicon carbidecoated graphite,RF Coil,Gas in,Gas exit,Silicon carbidesusceptor,Gas exit,Siliconwafers,RF inductionheating coil,Dry Etching System - 1,28,QuartzSiliconSilicon carbideRF,(a) Sputtering Etching,(b) Plasma Etching,(c) Reactive Ion Etching,Ion,Reactive Ion,VolatileP
18、roduct,VolatileProduct,Reactive Ion,RIE,29,(a) Sputtering Etching (b) Pl,Scheme Diagram of RIE System,Gas In,To Vacuum Pump,Plasma,Electrode,RF,30,Scheme Diagram of RIE SystemG,Annealing,SiO2 Post Ion Implantation Annealing,RTPRAPID THERMAL PROCESS快速升温过程,31,Annealing SiO2RTP31,Furnace,Reaction Room,
19、Gas in (H2),Wafer,3-Zone Heating Element,Gas out,Gas in (O2),Loading Area,32,FurnaceReaction RoomGas in (H2,Rapid Thermal Processing,T/s 100 C/s Uniform Temperature Changing Low Thermal Budget (to compare with Furnace) To Avoid MOS Distortion,33,Rapid Thermal Processing T/s,Halogen-W Heater (vertical),Halogen-W Heater (horizontal),Wafer,Gas out,Gas in,Typical RTP System,Quartz Shelf,34,Halogen-W Heater (vertical)Hal,The End,Thank you!,35,The EndThank you!35,
