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1、第五部分：F2812 时钟与控制系统,C28x GPIO 寄存器结构,C28x GPIO 引脚分配,Note: GPIO are pin functions at reset,GPIO A, B, D, E includeInput Qualification feature,C28x GPIO 功能框图,1,0,MUX Control Bit0 = I/O Function1 = Primary Function,Pin,PrimaryPeripheralFunction,I/O DATBit (R/W),In,Out,I/O DIR Bit0 = Input1 = Output,GPxMU
2、X,GPxDIR,GPxDAT,GPxSETGPxCLEARGPxTOGGLE,Some digital I/O andperipheral I/O inputsignals include an Input Qualificationfeature,C28x GPIO MUX/DIR 寄存器,C28x GPIO 数据寄存器,C28x Osc / PLL 时钟模块PLLCR 7021h,PLLCRbits 15:4reserved,crystal,PLLClock Module4-bit PLL Select,X1 /CLKIN,X2,XTAL OSC,WatchdogModule,PLLCL
3、K,OSCCLK,C28xCore,CLKIN,MUX,XF_XPLLDIS,1,0,SYSCLKOUT,HSPCLK,LSPCLK,1、PLL旁路2、PLL使能,外设时钟控制寄存器PCLKCR 701Ch,高/低速外设时钟预定标寄存器HISPCP 701Ah / LOSPCP 701Bh,看门狗定时器,如果CPU崩溃，则复位系统看门狗计数器独立与CPU如果计数器溢出则复位或中断被触发为防止计数器溢出，CPU必须周期性的向看门狗KEY寄存器写入0X55+0XAA序列在 复位之后 (30 M外部时钟)3ms之内看门狗必须被启用或者禁止,看门狗定时器模块,6 - BitFree -RunningC
4、ounter,CLR,/2,/4,/8,/16,/32,/64,OSCCLK,SystemReset,101,100,011,010,001,000,111,110,8 - Bit WatchdogCounter,CLR,One-CycleDelay,WatchdogReset KeyRegister,55 + AADetector,Good Key,Bad Key,1 0 1,/,/,3,3,WDCR . 2 - 0,WDCR . 6,WDPS,WDDIS,WDCR . 7,WDFLAG,WDCNTR . 7 - 0,WDKEY . 7 - 0,WDCR . 5 - 3,WDCHK 2-0,
5、Bad WDCR Key,OutputPulse,WDRST,WDINT,SCSR .1,WDENINT,SCSR . 0,WDOVERRIDE,看门狗定时控制寄存器 WDCR 7029h,WDFLAG,WDDIS,7,6,5,4,3,2,1,0,WDCHK1,WDCHK0,WDPS2,WDPS1,WDPS0,WDCHK2,Logic Check BitsWrite as 101 or reset immediately triggered,WD PrescaleSelection Bits,Watchdog Disable Bit(Functions only if WD OVERRIDEb
6、it in SCSR is equal to 1),reserved,15 - 8,WD Flag BitGets set when the WD causes a reset Writing a 1 clears this bit Writing a 0 has no effect,看门狗复位密钥寄存器 WDKEY 7025h,允许写入的数值:55h 在AAH之后的写入55使能计数器AAh 如果复位使能则计数器清零写入其他任何值将复位CPU,reserved,D7,7,6,5,4,3,2,1,0,D6,D5,D4,D3,D2,D1,D0,15 - 8,WDKEY 写操作,Sequential
7、Step1234567891011,Value Writtento WDKEYAAhAAh55h55h55hAAhAAh55hAAh55h23h,ResultNo actionNo actionWD counter enabled for reset on next AAh writeWD counter enabled for reset on next AAh writeWD counter enabled for reset on next AAh writeWD counter is resetNo actionWD counter enabled for reset on next
8、AAh writeWD counter is resetWD counter enabled for reset on next AAh writeCPU reset triggered due to improper write value,系统控制和状态寄存器SCSR 7022h,WD Enable Interrupt,WD Interrupt Status(read only),0 = active1 = not active,0 = WD generates a DSP reset1 = WD generates a WDINT interrupt,低功耗模式,Low PowerMod
9、e,CPU LogicClock,PeripheralLogic Clock,WatchdogClock,PLL /OSC,Normal RunIDLESTANDBYHALT,onoffoffoff,ononoffoff,onononoff,onononoff,低功耗方式控制0寄存器LPMCR0 701Eh,Low Power Mode Selection,00 = Idle01 = Standby1x = Halt,低功耗模式控制1寄存器LPMCR1 701Fh,0,WDINT,SCIRXB,C2TRIP,C5TRIP,T3CTRIP,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,XINT1,XNMI,T2CTRIP,T1CTRIP,C3TRIP,T4CTRIP,C4TRIP,C1TRIP,C6TRIP,SCIRXA,CANRXA,IDLESTANDBYHALT,ExitInterrupt,Low PowerMode,EnabledPeripheralInterrupts,Note: External or Wake up include XINT1, PDPINT, TxCTRIP, CxTRIP NMI, CAN, SPI, SCI, WD,低功耗模式退出,
