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1、Chapter 7sequential logic design principles,state,state variablelatches,flip-flopsanalysissynthesis,sequential circuit,the outputs depend not only on its current inputs,but also on the past sequence of time,possibly arbitrarily far back in time.,Some important concepts,state and state variable state
2、:collection of state variable,contain all the information about the past necessary to account for the circuits future behavior.state variable:the symbol representation of state.finite-state machine the states of a sequential circuit is always finite.,n state variables,2n possible states,Some importa
3、nt concepts,clock a clock signal is a signal used to coordinate the actions of two or more sequential units.clocked synchronous state machine all memory of the sequential circuit changes only on a clock edge or signal level.,H,L,7.1 Bistable Element,Output variable：Q，Q_L，且Q_L=QTwo stable state:Q=0、Q
4、_L=1 Q=1、Q_L=0,feedback,1,2,Q is the state variable,analysis with transfer characteristic,VOUT=T(VIN),VIN,VOUT,7.2 Latches and Flip_Flops,basic building blockbe classified as S-R、D、T、J-K typesdefinition:latch：watches the circuits inputs continuously and can changes the outputs at any time.flip-flops
5、：samples the circuits inputs and changes the output only when a clocking signal is changing.,1、SR Latches,S-R latch built with NOR gates,Q=QN=Q_L,hold,reset,set,forbidden,1,2,the stored bit is present on the output Q.,S and R:active high signal,Function table,进入亚稳态,(2)minimum pulse width,the time of
6、 active level of S or R must be keeping longer than minimum pulse width,or else the latch may be go into metastable.,propagation delay is exist when a transition on S or R input produce a transition on an output signal.,S,(3)symbol and characteristic equation,S=R=1,restricted combination,characteris
7、tic equation for S-R latch:Q*=S+RQ（SR=0）,current state,next state,2、S-R latch,built with NAND gates,S_L、R_L:active low signals,hold,reset,set,forbidden,3、S-R latch with enable,metastable still exist,forbidden,4、D latch,保持,R,S,characteristic equation Q*=D（C=1）transfer data transparently,when C=0，the
8、data is latched on Q.,timing diagram,data transfered,data latched,5、Edge-Triggered D Flip-Flops,Edge-Triggered：output of flip-flop changes on the clock signals rising edge or falling edge.,positive edge（rising edge）,negative edge（falling edge）,CLOCK,positive-edge-triggered D flip-flop,master-slave s
9、tructureCLK=0，QM=D，US hold last Q；At the clocks rising edge,US enable，UM hold last QM，Q=QM；CLK=1，UM hold last QM，so Q hold last Q。,UM,US,Only at the rising edge of clock signal,D input could be transferred to Q output.,Others,PR_L:presetCLR:clear,Negative-edge-triggered D flip-flop,edge-triggered D
10、flip-flop with asynchronous inputs,6、edge-triggered D flop-flop with enable,characteristic equation：Q*=END+ENQ,frequency divider with D f-fs,divide-by-2 divider,7、scan flip-flop,TE=1，test operation mode，f-fs take TI data.TE=0，normal D f-f-s，take D data.,Normal input,Test enable,Test input,8、master/s
11、lave S-R触发器,Q*=S+RQ（SR=0）C=1,master latch follows the S-R input;C goes to 0,Q output the final latched value of master latch.It is not edge-triggered f-fs,but pulse-triggered.,C,S,R,QM,QM_L,Q,Q_L,Timing diagram of S-R f-fs,9.master/slave J-K flip-flop,stucture,J,K,C,Q,Q_L,feedback,C=1，master latch f
12、ollow the input;C goes to 0,Q output(slave latch)the final latch value.,Master,Slave,JK flip-flop timing diagram,J,K,C,Q,Q_L,C,J,K,QM,QM_L,Q,Q_L,features,reset,set,toggle,hold,Pulse-triggered f-f-s,Characteristic equations：Q*=JQ+KQ,Eliminate the possible metastable which exist in the S-R f-fs(restri
13、cted input,S=R=1).But,1s catching and 0s catching are exist.,hold,1s catching,C=1，当上次Q=0，当前JK=0时，若J有1的出现，触发器会捕捉到这一变化，置Q=1。以后，J有1到0的变化，电路不会响应。,0s catching,当上次Q=1，当前JK=0时，若K有1的出现，触发器会捕捉到这一变化，置Q=0。以后，K有1到0的变化，电路不会响应。,10、Edge-triggered J-K Flip-Flop,sample the inputs and change the output state at the e
14、dge of clock。characteristic equations：Q*=JQ+KQ eliminate the“1s catching”and“0s catching”.,Timing diagram of edge-triggered J-K f-fs,11、T Flip-Flop,T:toggle functional table,symbol,characteristic equation：Q*=TQ+TQ,Implementation,Contribute by D or J-K f-fs.,T Flip-Flop with enable,EN=1，normal T flip
15、-flop;EN=0，hold the last value,summary:latches and flip-flops,label by structure：latches：S-R、D latches flip-flops：S-R、D、J-K、T flip-flopslabel by triggering form：pulse-triggered、edge-triggeredone latch or flip-flop is a storage elements,which can store one bit(0 or 1).it also act as a state variable,
16、and more storage elements can be combined to store more bits which used to memory states in sequential circuit.,summary:characteristic equation,S-R latchD latchD flip-flopD flip-flop with enableM/S S-R flip-flopM/S J-K flip-flopedge-triggered J-K flip-flopT flip-flop,Q*=S+RQ（SR=0）Q*=DQ*=DQ*=END+ENQQ
17、*=S+RQ（SR=0）Q*=JQ+KQQ*=JQ+KQQ*=TQ+TQ,7.3 clocked synchronous state-machine analysis,emphases：Basic structureMealy machine and Moore machine.understand action of each module and their equations,tables.analysis with D f-fs,1、stucture,（1）Mealy machine,Next-state logicF,state memoryclock,Output logicG,i
18、nputs,excitation,Current state,outputs,Clock signal,construct by combinational circuit,the output signal is the excitation input of storage element.next state=F(current state,input),construct by flip-flops,can store 2n state at most,construct by combinational circuit,output=G(current state,input),返回
19、,（2）Moore machine,Next-state logic F,state memory clock,Output logicG,PS:output=G(current state),inputs,Clock signal,excitation,Current state,outputs,2.analysis example,state variable：Q0、Q1,excitation：D0、D1,output：MAX,D0=F（EN，Q1，Q0）=(ENQ0)+(ENQ0)=ENQ0+ENQOD1=F（EN，Q1，Q0）=ENQ1+ENQ1Q0+ENQ1Q0,excitation
20、 equation,Characteristic equation of D f-fs：Q*=D,Transition equation：Q1*=D1=ENQ1+ENQ1Q0+ENQ1Q0Q0*=D0=ENQ0+ENQO,transition equation,Transition table and state table,Transition equation：Q1*=ENQ1+ENQ1Q0+ENQ1Q0Q0*=ENQ0+ENQO,Transition table,State table,Assign state name to each state:Q1Q0 S 00 A 01 B 10
21、 C 11 D,Current state,input,Next state,MAX=ENQ1Q0,Output equation,EN,MAX,Transition/output table,state/output table,Transition/output table,state/output table,A,D,C,B,State diagram,Q1Q0,State variable combination can be write in the circle directly.,注意：有限状态机的时序分析必须以时钟周期为单位依序进行。,Timing diagram,Analys
22、is of Moore maching,excitation equation and transition equation are changeless,MAXS=Q1Q0,transition table,state table,AMAXS=0,DMAXS=1,C MAXS=0,BMAXS=0,EN=0,EN=1,EN=0,EN=1,EN=0,EN=1,EN=0,EN=1,show output value inside the circle,state diagram,例1、2的时序对比分析,state transition feature,transition expression
23、on arcs leaving a particular state must be mutually exclusive and all inclusive.No two transition expressions can equal 1 for the same input combination;For every possible input combination,some transition expression must equal 1.,S1,I1,Si,S1,Sn,Ii,In,transition expression,3、analysis with J-K flip-f
24、lops,(1)excitation equation：J0=K0=1J1=K1=XQ0,(2)transition equation:Q0*=J0Q0+K0Q0=Q0Q1*=J1Q1+K1Q1=XQ0Q1,(3)output equation：Z=Q0Q1,(4)transition/output table and state/output table,assign state name：Q1Q0 S 00 A 01 B 10 C 11 D,AZ=0,DZ=1,C Z=0,BZ=0,X=1,X=0,X,X,X,X,X,X,state diagram,CP,timing diagram,X,
25、Q1,Q0,Z,Exp3：analyze the following circuit,X,CLK,Z,(1)excitation equation：T1=XT2=XQ1,T1,T2,Q1,Q2,(2)transition equation：Q1*=T1Q1+T1Q1=XQ1+XQ1Q2*=T2Q2+T2Q2=XQ1Q1+（XQ1）Q1,(3)output equation：Z=XQ1Q2,7.4 clocked synchronous state-machine design,Construct state/output table,State minimization（可选）,State a
26、ssignment,Construct transition/output table,Choose flip-flops,Construct excitation table,Deriving excitation equation,Deriving output equation,Drawing logic circuit diagram,Exp1:sequence-detector design,Design a“110”sequence-detector.if the serial input binary number include continuous“110”sequence,
27、the circuit output 1.synthesis by D flip-flops.that is input P：output C：solution 1：Moore machine（1）input and output variable input：P（每次给电路送一个二进制数码）output：C（表明检测的结果，1位）,first input,state analysis of exp.1,P：,C：,目标：检测110,Input 0,Input 1,Exp1:sequence-detector design,Defining state：S0 received a single
28、 0S1 received a single 1S2 received a continuous“11”S3received a continuous“110”,state/output table,（2）state minimization（3）state assignment（状态的分配、赋值）n state variables 2n states。Then,S states need(?)state variables(flip-flops)to represent.The number of f-fs：m=2，named Q0、Q1Assign state variable combi
29、nations to each symbol state：S：S0 S1 S2 S3 Q1Q0：00 01 10 11,Use state combinations to substitute the symbol state.,(4)construct transition/output table,S0,S1,S2,S3,(5)Construct excitation table,Choose flip-flops and use application equation to construct excitation table.,Function table of D f-f-s,Ap
30、plication table,Excitation table,Application equation：D=Q*,D1=Q1Q0+Q1Q0PD0=Q1Q0P+Q1Q0P+Q1Q0P,(6)Derive the excitation equations,C=Q1Q0,(7)Derive the output equation,思考：若状态赋值时，采用gray码顺序给各状态赋值，则电路是怎样的？,（1）defining statesS0receive a single 0，C=0S1receive a single 1，C=0S2receive continuous“11”，C=0S3rece
31、ive continuous“110”，C=1,Solution 2:use mealy machine,(2)Construct state/output table,S0 and S3 are equivalent states，so eliminate S3,and get the minimized state/output table.,S0,(3)State minimization,Number of f-fs：named Q1、Q0Q1Q0=00，01，10，11 choose 3 to assign to the 3 known states。like，S0 00，S1 01
32、，S2 11Q1Q0=10，unused state.,Transition/output table,(4)State assignment,minimal risk,minimal cost,Disposition of unused states,(5)Construct excitation table,Use D f-fs and in minimal cost disposition.,Excitation table,Application equation：D=Q*,(6)Derive the excitation equations and output equation,D
33、1=Q0PD0=PC=Q1P,another way:synthesis using J-K f-fs,Application table of J-K f-fs,Excitation table,Minimal cost disposition,Excitation equations J1=PQ0 K1=P J0=P K0=Poutput equation C=Q1P,Excitation equations and output equation,课堂练习,试写出如下电路的激励方程和转移方程。,D1=XQ0Q1D0=XQ0+Q1Q1*=D1Q0*=D0Y=X+Q1Q0,Design ex
34、amples in book,Exp1:Design a machine inputs A and B with output Z that is 1 if:A had the same value at the two previous ticksB has been 1 since the last time the above was true）,CLK,A,B,Z,At the beginning,set state INIT，Z=0状态A0，A收到一个0，Z=0状态A1，A收到一个1，Z=0状态OK0，A收到连续的两个0，Z=1状态OK1，A收到连续的两个1，Z=1状态A001，A收
35、到连续的两个0后，收到1，同时B=1，Z=1状态A110，A收到连续的两个1后，收到0，同时B=1，Z=1状态AE10，A已经收到过连续的00或11，收到连续的10，同时B=1，Z=1状态AE01，A已经收到过连续的00或11，收到连续的01，同时B=1，Z=1,1.Find states,电路开始工作，设置INIT状态，Z=0状态A0，A收到第一个0，Z=0状态A1，A收到第一个1，Z=0状态OK0，A收到连续的两个0，Z=1状态OK1，A收到连续的两个1，Z=1状态A001，A收到连续的两个0后，收到1，同时B=1，Z=1状态A110，A收到连续的两个1后，收到0，同时B=1，Z=1状态A
36、E10，A已经收到过连续的00或11，收到连续的10，同时B=1，Z=1状态AE01，A已经收到过连续的00或11，收到连续的01，同时B=1，Z=1,Equivalent states,eliminate state AE10,Equivalent states，eliminate state AE01,State minimization,Equivalent states,eliminate state A001,Equivalent states，eliminate state A110,State minimization,最小化状态个数的状态表,Minimal state tabl
37、e,State assignment,Possible state assignments,Q1=0,in the INIT stateQ1=1,in the non-INIT state,In the non-INIT state,Q3 give the previous value of A;Q2 indicates that the conditions for a 1 output are satisfied in the current state.,Transition table and excitation table,？,Completed excitation table,
38、Two approaches:Minimal costMinimal risk,Disposition of unused states,D1,Minimal risk,D1=Q1+Q2Q3D2,D3,Z=Q1Q2,D1,Minimal cost,D1=1D2,D3,Z=Q2,Logic diagram in minimal cost for Exp1,Logic diagram in minimal risk for Exp1,Exp2:1s-counting machine,design a clocked synchronous state-machine with two inputs
39、 X and Y,and one output Z,the output should be 1 if the number of 1 inputs on X and Y since reset is a multiple of 4,and 0 otherwise.,reset,Each state record the number of 1 input on X and Y：Multiple of 4 imply that the number of 1 input can be divided by 4.(MOD 4=0)N MOD 4=0，Z=1 S0N MOD 4=1，Z=0 S1N
40、 MOD 4=2，Z=0 S2N MOD 4=3，Z=0 S3,Naming state,Synthesis steps,1、state/output table,2、state assignment:S0 00、S1 01、S2 11、S3 10,3、transition/output table,4、application table,Exp3:a combination lock,requirement:UNLK=1 if and only if X is 0 and the sequence of inputs received on X at the preceding seven
41、clock ticks of X was 0110111.HINT=1 if and only if the current value of X is the correct one to move the machine closer to being in the“unlocked”state(with UNLK=1).It is a sequence-detector machine,7.5 designing state machines using state diagram,Difference between state table and state diagram desi
42、gn：状态表是穷举列表的方法状态图表达状态的转移用一条带转移表达式的弧线，其中可能包含多个输入。经常不能一次达到状态转移的完备性。,Exp1:a sequence-detector,if the serial input bits are continuous“1101”,then output 1.,S0,S1,S11,S110,Receive first 1,Receive continuous 11,Receive continuous 110,S1101,Receive a single 0,Receive continuous 1101,状态图中的等价状态的判断：观察是否有两个状态的
43、离开弧线有相同的转移表达式并值相同一个状态，如果是，则两个状态是等价状态。本例中S0和S1101是等价状态。状态赋值并建立转移/输出表及激励表：,S0,S1,S11,S110,Excitation equation：D1=Q1Q0+Q0X D2=Q1X+Q0XOutput equation：Z=Q1Q0X,例2、雷鸟车尾灯的状态机,input：L（LEFT）、R（RIGHT）、H（HAZ）output：LA、LB、LC、RA、RB、RCWorking condition：input L LA、LB、LC lighting on successively and off input R RA、R
44、B、RC lighting on successively and off；input H all lights flashing on and off no input,all lights off.,LA,LB,LC,RA,RB,RC,First State diagram,IDLE,LR3,L1,L3,L2,R1,R3,R2,Some faulty aspectThinking carefully,IDLE,LR3,L1,L3,L2,R1,R3,R2,H+LR,1,HLR,Corrected diagram,IDLE,LR3,L1,L3,L2,R1,R3,R2,H+LR,H,H,H,H,
45、1,HLR,H,H,H,H,Corrected diagram again,State assignment,8 states，need 3 f-fs，so named Q0、Q1、Q2。Assign state：S IDLE L1 L2 L3 R1 R2 R3 LR3 Q2Q1Q0 000 001 011 010 101 111 110 100Construct transition list（p.427 表7-17）Derive transition equation：转移列表视为真值表，其中，当前态Q2、Q1、Q0和转移表达式作为输入，次态Q2*、Q1*、Q0*作为输出。,课堂练习,已知某同步时序电路的转移方程、输出方程如下，请写出其转移/输出表，并画出状态图，试说明其功能。状态变量赋值按Q1Q0=00、01、10、11。Q1*=XQ0Q1+XQ1Q0*=XQ0+XQ1Q0Y=Q0Q1,
