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1、MonolithIC 3D Inc.,Patents Pending,MonolithIC 3D ICs,February 2013,1,MonolithIC 3D Inc.,Patents Pending,Content,Chapter 1 MonolithIC 3D Chapter 2 Laser AnnealingChapter 3-Monolithic 3D RCATChapter 4-Monolithic 3D HKMGChapter 5-Monolithic 3D RC-JLT Chapter 6-Monolithic 3D eDRAM on LogicChapter 7-The
2、Monolithic 3D AdvantageChapter 8 Monolithic 3D DRAM,MonolithIC 3D Inc.Patents Pending,2,MonolithIC 3D Inc.Patents Pending,3,Chapter 1Monolithic 3D,3D ICs at a glance,A 3D Integrated Circuit is a chip that has active electronic components stacked on one or more layers that are integrated both vertica
3、lly and horizontally forming a single circuit.Manufacturing technologies:MonolithicTSV based stackingChip Stacking w/wire bonding,MonolithIC 3D Inc,Patents Pending,4,MonolithIC 3D,A technology breakthrough allows the fabrication of semiconductor devices with multiple thin tiers(1um)of copper connect
4、ed active devices utilizing conventional fab equipment.MonolithIC 3D Inc.offers solutions for logic,memory and electro-optic technologies,with significant benefits for cost,power and operating speed.,MonolithIC 3D Inc.,Patents Pending,5,Comparison of Through-Silicon Via(TSV)3D Technology and Monolit
5、hic 3D Technology,The semiconductor industry is actively pursuing 3D Integrated Circuits(3D-ICs)with Through-Silicon Via(TSV)technology(Figure 1).This can also be called a parallel 3D process.As shown in Figure 2,the International Technology Roadmap for Semiconductors(ITRS)projects TSV pitch remaini
6、ng in the range of several microns,while on-chip interconnect pitch is in the range of 100nm.The TSV pitch will not reduce appreciably in the future due to bonder alignment limitations(0.5-1um)and stacked silicon layer thickness(6-10um).While the micron-ranged TSV pitches may provide enough vertical
7、 connections for stacking memory atop processors and memory-on-memory stacking,they may not be enough to significantly mitigate the well-known on-chip interconnect problems.Monolithic 3D-ICs offer through-silicon connections with 50nm diameter and therefore provide 10,000 times the areal density of
8、TSV technology.,MonolithIC 3D Inc.,Patents Pending,6,MonolithIC 3D Inc.Patents Pending,7,Typical TSV process,TSV diameter typically 5um Limited by alignment accuracy and silicon thickness,Processed Top Wafer,Processed Bottom Wafer,Align and bond,Figure 1,Two Types of 3D Technology,8,3D-TSVTransistor
9、s made on separate wafers high temp.,then thin+align+bond,TSV pitch 1um*,Monolithic 3DTransistors made monolithically atop wiring(sub-400oC for logic),TSV pitch 50-100nm,10um-50um,100 nm,*Reference:P.Franzon:Tutorial at IEEE 3D-IC Conference 2011,Figure 2ITRS Roadmap compared to monolithic 3D,Monoli
10、thIC 3D Inc.,Patents Pending,9,TSV(parallel)vs.Monolithic(sequential),MonolithIC 3D Inc.,Patents Pending,10,Source:CEALetiSemiconWest2012presentation,The Monolithic 3D Challenge,Once copper or aluminum is added on for bottom layer interconnect,the process temperatures need to be limited to less than
11、 400C!Forming single crystal silicon requires 1,200CForming transistors in single crystal silicon requires 800CThe TSV solution overcame the temperature challenge by forming the second tier transistors on an independent wafer,then thinning and bonding it over the bottom wafer(parallel)The limitation
12、s:Wafer to wafer misalignment 1Overlaying wafer could not be thinned to less than 50,The Monolithic 3D Innovation,Utilize Ion-Cut(Smart-Cut)to transfer a thin(100nm)single crystal layer on top of the bottom(base)waferForm the cut at less than 400C*Use co-implantUse mechanically assisted cleavingForm
13、 the bonding at less than 400C*See details at:Low Temperature Cleaving,Low Temperature Wafer Direct BondingSplit the transistor processing to two portionsHigh temperature process portion(ion implant and activation)to be done before the Ion-CutLow temperature(400C)process portion(etch and deposition)
14、to be done after layer transferSee details in the following slides:,Monolithic 3D ICs,Using SmartCut technology-the ion cutting process that Soitec uses to make SOI wafers for AMD and IBM(millions of wafers had utilized the process over the last 20 years)-to stack up consecutive layers of active sil
15、icon(bond first and then cut).Soitecs Smart Cut Patented*Flow(follow this link for video).,MonolithIC 3D Inc.,Patents Pending,13,*Soitecs fundamental patent US 5,374,564 expired Sep.15,2012,Monolithic 3D ICs,Ion cutting:the key idea is that if you implant a thin layer of H+ions into a single crystal
16、 of silicon,the ions will weaken the bonds between the neighboring silicon atoms,creating a fracture plane(Figure 3).Judicious force will then precisely break the wafer at the plane of the H+implant,allowing you to in-effect peel off very thin layer.This technique is currently being used to produce
17、the most advanced transistors(Fully Depleted SOI,UTBB transistors Ultra Thin Body and BOX),forming monocrystalline silicon layers that are less than 10nm thick.,MonolithIC 3D Inc.,Patents Pending,14,Figure 3Using ion-cutting to place a thin layer of monocrystalline silicon above a processed(transist
18、ors and metallization)base wafer,MonolithIC 3D Inc.,Patents Pending,15,p-Si,Oxide,p-Si,Oxide,H,Top layer,Bottom layer,Oxide,Hydrogen implant of top layer,Flip top layer and bond to bottom layer,Oxide,p-Si,Oxide,H,Cleave using 400oC anneal or sideways mechanical force.CMP.,Oxide,Oxide,Similar process
19、(bulk-to-bulk)used for manufacturing all SOI wafers today,p-Si,MonolithIC 3D Inc.Patents Pending,16,Chapter 2Laser Annealing,17,FD-SOI with Shielding Layers,MonolithIC 3D Inc.Patents Pending,Base Wafer,Oxide-oxide bond,Transferred Donor Layer,Shielding Layers,MonolithIC 3D Inc.,Patents Pending,Excim
20、er Laser 3D Annealing:Equipment available,18,MonolithIC 3D Inc.,Patents Pending,The 3D Thermal Processes Challenge,SEMI&PV trends,Cost reductionYield increaseNew Material2D to 3D,Minimize StepsProcess uniformityMaterial selectivityLow thermal Budget,Process Flow,+Pulsed Lasers+Wavelength selectivity
21、+Single Die Anneal,From EXCICO,19,Activation of FD-SOI without Heating the Underneath Layers,MonolithIC 3D Inc.Patents Pending,Base Wafer,Oxide-oxide bond,Transferred Donor Layer,Shielding Layers,MonolithIC 3D Inc.,Patents Pending,Laser Pulse,MonolithIC 3D Inc.Patents Pending,20,Chapter 3Monolithic
22、3D RCAT,MonolithIC 3D The RCAT path,The Recessed Channel Array Transistor(RCAT)fits very nicely into the hot-cold process flow partitionRCAT is the transistor used in commercial DRAM as its 3D channel overcomes the short channel effect Used in DRAM production 90nm,60nm,50nm nodesHigher capacitance,b
23、ut less leakage,same drive currentThe following slides present the flow to process an RCAT without exceeding the 400C temperature limit,MonolithIC 3D Inc.,Patents Pending,21,RCAT a monolithic process flow,MonolithIC 3D Inc.,Patents Pending,22,Wafer,700m,100nm,P-,N+,P-,Using a new wafer,construct dop
24、ant regions in top 100nm and activate at 1000C,Oxide,MonolithIC 3D Inc.Patents Pending,23,100nm,P-,N+,P-,Oxide,Implant Hydrogen for Ion-Cut,H+,Wafer,700m,MonolithIC 3D Inc.Patents Pending,24,100nm,P-,N+,P-,10nm,Oxide,Hydrogen cleave plane for Ion-Cut formed in donor wafer,Wafer,700m,MonolithIC 3D In
25、c.Patents Pending,25,100nm,N+,P-,Oxide,1 Top Portion ofBase Wafer,Flip over and bond the donor wafer to the base(acceptor)wafer,Base Wafer,700m,Donor Wafer,700m,MonolithIC 3D Inc.Patents Pending,26,100nm,N+,P-,Oxide,1 Top Portion ofBase Wafer,Perform Ion-Cut Cleave,Base Wafer 700m,27,100nm,N+,P-,Oxi
26、de,1 Top Portion ofBase Wafer,MonolithIC 3D Inc.Patents Pending,Complete Ion-Cut,Base Wafer 700m,28,100nm,N+,P-,Oxide,1 Top Portion ofBase Wafer,MonolithIC 3D Inc.Patents Pending,Etch Isolation regions as the first step to define RCAT transistors,Base Wafer 700m,29,100nm,N+,P-,Oxide,1 Top Portion of
27、Base Wafer,MonolithIC 3D Inc.Patents Pending,Fill isolation regions(STI-Shallow Trench Isolation)with Oxide,and CMP,Base Wafer 700m,30,100nm,N+,P-,Oxide,1 Top Portion ofBase Wafer,MonolithIC 3D Inc.Patents Pending,Etch RCAT Gate Regions,Base Wafer 700m,Gate region,31,100nm,N+,P-,Oxide,1 Top Portion
28、ofBase Wafer,MonolithIC 3D Inc.Patents Pending,Form Gate Oxide,Base Wafer 700m,32,100nm,N+,P-,Oxide,1 Top Portion ofBase Wafer,MonolithIC 3D Inc.Patents Pending,Form Gate Electrode,Base Wafer 700m,33,100nm,N+,P-,Oxide,1 Top Portion ofBase Wafer,MonolithIC 3D Inc.Patents Pending,Add Dielectric and CM
29、P,Base Wafer 700m,34,100nm,N+,P-,Oxide,1 Top Portion ofBase Wafer,MonolithIC 3D Inc.Patents Pending,Etch Thru-Layer-Via and RCAT Transistor Contacts,Base Wafer 700m,35,100nm,N+,P-,Oxide,1 Top Portion ofBase Wafer,MonolithIC 3D Inc.Patents Pending,Fill in Copper,Base Wafer 700m,36,100nm,N+,P-,Oxide,1
30、 Top Portion ofBase(acceptor)Wafer,MonolithIC 3D Inc.Patents Pending,Add more layers monolithically,Base Wafer 700m,Oxide,100nm,N+,P-,MonolithIC 3D Inc.Patents Pending,37,Chapter 4Monolithic 3D HKMG,MonolithIC 3D Inc.Patents Pending,38,The monolithic 3D IC technology is appliedto produce monolithica
31、lly stacked highperformance High-k Metal Gate(HKMG)devices,the worlds most advancedproduction transistors.3D Monolithic State-of-the-Art transistorsare formed with ion-cut applied to a gate-lastprocess,combined with a low temperatureface-up layer transfer,repeating layouts,andan innovative inter-lay
32、er via(ILV)alignmentscheme.Monolithic 3D IC provides a path to reducelogic,SOC,and memory costs withoutinvesting in expensive scaling down.,Technology,MonolithIC 3D Inc.Patents Pending,39,700m Donor Wafer,On the donor wafer,fabricate standard dummy gates with oxide and poly-Si;900C OK,PMOS,NMOS,Sili
33、con,PolyOxide,MonolithIC 3D Inc.Patents Pending,40,700m Donor Wafer,Form transistor source/drain,PMOS,NMOS,Silicon,PolyOxide,MonolithIC 3D Inc.Patents Pending,41,700m Donor Wafer,PMOS,NMOS,Silicon,Form inter layer dielectric(ILD),do high temp anneals,CMP near to transistor tops,CMP near to top of du
34、mmy gates,ILD,S/D Implant,MonolithIC 3D Inc.Patents Pending,42,700m Donor Wafer,PMOS,NMOS,Silicon,Implant hydrogen to generate cleave plane,MonolithIC 3D Inc.Patents Pending,43,700m Donor Wafer,PMOS,NMOS,Silicon,Implant hydrogen to generate cleave plane,MonolithIC 3D Inc.Patents Pending,44,700m Dono
35、r Wafer,PMOS,NMOS,Silicon,Implant hydrogen to generate cleave plane,H+,MonolithIC 3D Inc.Patents Pending,45,700m Donor Wafer,Silicon,Bond donor wafer to carrier wafer,H+,700m Carrier Wafer,MonolithIC 3D Inc.Patents Pending,46,700m Donor Wafer,Cleave to remove bulk of donor wafer,H+,700m Carrier Wafe
36、r,Transferred Donor Layer(nm scale),Silicon,Silicon,MonolithIC 3D Inc.Patents Pending,47,CMP to STI,700m Carrier Wafer,STI,Transferred Donor Layer(100nm),MonolithIC 3D Inc.Patents Pending,48,Deposit oxide,ox-ox bond carrier structure to base wafer that has transistors&circuits,700m Carrier Wafer,STI
37、,Oxide-oxide bond,PMOS,NMOS,700mBase Wafer,Transferred Donor Layer(100nm),49,Remove carrier wafer,Oxide-oxide bond,700m Carrier Wafer,MonolithIC 3D Inc.Patents Pending,PMOS,NMOS,700mBase Wafer,Transferred Donor Layer(100nm),50,Carrier wafer had been removed,Oxide-oxide bond,MonolithIC 3D Inc.Patents
38、 Pending,PMOS,NMOS,700mBase Wafer,Transferred Donor Layer(100nm),51,CMP to expose gate stacks.Replace dummy gate stacks with Hafnium Oxide&Metal(HKMG)at low temp,Oxide-oxide bond,MonolithIC 3D Inc.Patents Pending,PMOS,NMOS,Note:Replacing the gate oxide and gate electrode results in a gate stack that
39、 is not damaged by the H+implant,700mBase Wafer,Transferred Donor Layer(100nm),52,Form inter layer via(ILV)through oxide only(similar to standard via),Oxide-oxide bond,MonolithIC 3D Inc.Patents Pending,PMOS,NMOS,Note:The second mono-crystal layer is very thin(100nm)and has a vertical oxide corridor;
40、hence,the via through it(TLV)may be constructed and sized similarly to other vias in the normal metal stack.,Transferred Donor Layer(100nm),700mBase Wafer,MonolithIC 3D Inc.Patents Pending,53,Form top layer interconnect and connect layers with inter layer via,Oxide-oxide bond,MonolithIC 3D Inc.Paten
41、ts Pending,PMOS,NMOS,ILV,Transferred Donor Layer(100nm),700mBase Wafer,MonolithIC 3D Inc.Patents Pending,54,Maximum State-of-the-Art transistorperformance on multi-strata2x lower power2x smaller silicon area4x smaller footprintPerformance of single crystal silicontransistors on all layers in the 3DI
42、CScalable:scales normally withequipment capabilityForestalls next gen litho-tool riskHigh density of vertical interconnectsenable innovative architectures,repair,and redundancy,Benefits for RCAT and HKMG,MonolithIC 3D Inc.Patents Pending,55,Chapter 5 Monolithic 3D RC-JLT(Recessed-Channel Junction-Le
43、ss Transistor),MonolithIC 3D Inc.Patents Pending,56,Monolithic 3D IC technology is applied toproducing monolithically stacked low leakageRecessed Channel Junction-Less Transistors(RC-JLTs).Junction-less(gated resistor)transistors arevery simple to manufacture,and they scaleeasily to devices below 20
44、nm:Bulk Device,not surfaceFully Depleted channelSimple alternative to FinFETSuperior contact resistance is achieved with theheavier doped top layer.The RCAT styletransistor structure provides ultra-low leakage.Monolithic 3D IC provides a path to reducelogic,SOC,and memory costs withoutinvesting in e
45、xpensive scaling down.,Technology,RCJLT a monolithic process flow,MonolithIC 3D Inc.,Patents Pending,57,Wafer,700m,100nm,P-,N+,N+,Using a new wafer,construct dopant regions in top 100nm and activate at 1000C,Oxide,MonolithIC 3D Inc.Patents Pending,58,100nm,P-,Oxide,Implant Hydrogen for Ion-Cut,H+,Wa
46、fer,700m,N+,N+,MonolithIC 3D Inc.Patents Pending,59,100nm,P-,10nm,Oxide,Hydrogen cleave plane for Ion-Cut formed in donor wafer,Wafer,700m,N+,N+,MonolithIC 3D Inc.Patents Pending,60,100nm,N+,N+,Oxide,1 Top Portion ofBase Wafer,Flip over and bond the donor wafer to the base(acceptor)wafer,Base Wafer,
47、700m,Donor Wafer,700m,P-,MonolithIC 3D Inc.Patents Pending,61,100nm,N+,N+,Oxide,1 Top Portion ofBase Wafer,Perform Ion-Cut Cleave,Base Wafer 700m,62,100nm,N+,N+,Oxide,1 Top Portion ofBase Wafer,MonolithIC 3D Inc.Patents Pending,Complete Ion-Cut,Base Wafer 700m,63,100nm,N+,N+,Oxide,1 Top Portion ofBa
48、se Wafer,MonolithIC 3D Inc.Patents Pending,Etch Isolation regions as the first step to define RCJLT transistors,Base Wafer 700m,64,100nm,N+,N+,Oxide,1 Top Portion ofBase Wafer,MonolithIC 3D Inc.Patents Pending,Fill isolation regions(STI-Shallow Trench Isolation)with Oxide,and CMP,Base Wafer 700m,65,
49、100nm,N+,N+,Oxide,1 Top Portion ofBase Wafer,MonolithIC 3D Inc.Patents Pending,Etch RCJLT Gate Regions,Base Wafer 700m,Gate region,66,100nm,N+,N+,Oxide,1 Top Portion ofBase Wafer,MonolithIC 3D Inc.Patents Pending,Form Gate Oxide,Base Wafer 700m,67,100nm,N+,N+,Oxide,1 Top Portion ofBase Wafer,Monolit
50、hIC 3D Inc.Patents Pending,Form Gate Electrode,Base Wafer 700m,68,100nm,N+,N+,Oxide,1 Top Portion ofBase Wafer,MonolithIC 3D Inc.Patents Pending,Add Dielectric and CMP,Base Wafer 700m,69,100nm,N+,N+,Oxide,1 Top Portion ofBase Wafer,MonolithIC 3D Inc.Patents Pending,Etch Thru-Layer-Via and RCJLT Tran
