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1、The Transistor Revolution,First transistorBell Labs,1948,Rabaey:Digital Integrated Circuits2nd,The First Integrated Circuits,Bipolar logic1960s,ECL 3-input GateMotorola 1966,Rabaey:Digital Integrated Circuits2nd,Intel 4004 Micro-Processor,19711000 transistors1 MHz operation,Rabaey:Digital Integrated
2、 Circuits2nd,Moores Law,Electronics,April 19,1965.,Rabaey:Digital Integrated Circuits2nd,Silicon IC processing,Similar to photographic printingExpose the silicon wafer through a mask Process the silicon waferRepeat sequentially to pattern all the layersLayout:A set of masks that tell a fabricator wh
3、at to pattern For each layer in your circuitLayers are metal,drain/source implants,gate,etc.You draw the layersSubject to vendor-supplied spacing rules,The wafer,Czochralski processMelt silicon at 1425 CAdd impurities(dopants)Spin and pull crystalSlice into wafers0.25mm to 1.0mm thickPolish one side
4、,Crystal and wafer,Wand(a finished 250lb crystal),A polished wafer,4X reticle,Wafer,The mask,Illuminate reticle on waferTypically 4 reductionTypical image is 2525mmLimited by focusStep-and repeat across waferLimited by mechanical alignment,Reference:FULLMAN KINETICS,Lithography,Patterning is done by
5、 exposing photoresist with lightRequires many steps per“layer”Example:Implant layer,Grow Oxide Layer,Reference:FULLMAN KINETICS,Reference:FULLMAN KINETICS,Add Photoresist,Reference:FULLMAN KINETICS,Mask,Reference:FULLMAN KINETICS,Animation,Reference:FULLMAN KINETICS,Reference:FULLMAN KINETICS,Refere
6、nce:FULLMAN KINETICS,Reference:FULLMAN KINETICS,9/03 IEEE spectrum,Patterning,How we pattern and expose the resistTo make the patterns we want on the silicon,IEEE Spectrum,7/99,p.41,9/03 IEEE spectrum,Detailed process sequence,1.Grow epi layerUltra-pure single-crystal silicon2.Implant n-well,Detaile
7、d process sequence(cont),3.Define active area4.Grow field oxideFor isolation,Detailed process sequence(cont),5.Grow gate oxide6.Pattern polysilicon,Detailed process sequence(cont),7.Form pFETs8.Form nFETs,Detailed process sequence(cont),9.Deposit LTO by CVD LTO is low-temperature oxideCVD is chemica
8、l vapor deposition10.Deposit Metal1Usually aluminum,Detailed process sequence(cont),11.Via definitionDeposit LTOMake via cuts12.Deposit Metal2Usually aluminum13.Overglass(not shown)Coat entire chip with Si3N4Make pad openings in Si3N4,An inverter,Figure courtesy Yan Borodovsky,Intel,A Pentium cutawa
9、y,National 0.18m process cutaway,Advanced Metallization-Copper,Copper versus Aluminum 40%lower resistivity 10 less electromigration,Interconnect Impact on Chip,Nature of Interconnect,Global Interconnect,Source:Intel,Permittivity,Projections,Simulated distribution of dopant atoms in a 0.05m nFETred:a
10、cceptor atomblue:donor atom,All figures from IEEE Spectrum,7/99,An AMD 50nm transistor,Frequency,P6,Pentium proc,486,386,286,8086,8085,8080,8008,4004,0.1,1,10,100,1000,10000,1970,1980,1990,2000,2010,Year,Frequency(Mhz),Lead Microprocessors frequency doubles every 2 years,Doubles every2 years,Courtes
11、y,Intel,Rabaey:Digital Integrated Circuits2nd,Power Dissipation,P6,Pentium proc,486,386,286,8086,8085,8080,8008,4004,0.1,1,10,100,1971,1974,1978,1985,1992,2000,Year,Power(Watts),Lead Microprocessors power continues to increase,Courtesy,Intel,Rabaey:Digital Integrated Circuits2nd,Power density,4004,8
12、008,8080,8085,8086,286,386,486,Pentium proc,P6,1,10,100,1000,10000,1970,1980,1990,2000,2010,Year,Power Density(W/cm2),Power density too high to keep junctions at low temp,Courtesy,Intel,Rabaey:Digital Integrated Circuits2nd,Productivity Trends,1,10,100,1,000,10,000,100,000,1,000,000,10,000,000,10,10
13、0,1,000,10,000,100,000,1,000,000,10,000,000,100,000,000,Logic Tr./Chip,Tr./Staff Month.,x,x,x,x,x,x,x,21%/Ypound,Productivity growth rate,x,58%/Ypounded,Complexity growth rate,Productivity(K)Trans./Staff-Mo.,Source:Sematech,Complexity outpaces design productivity,Complexity,Courtesy,ITRS Roadmap,Rab
14、aey:Digital Integrated Circuits2nd,Cost of Integrated Circuits,NRE(non-recurrent engineering)costsdesign time and effort,mask generationone-time cost factor Recurrent costssilicon processing,packaging,testproportional to volumeproportional to chip area,NRE Cost is Increasing,Rabaey:Digital Integrated Circuits2nd,Die Cost,Single die,Wafer,From http:/,Going up to 12”(30cm),Rabaey:Digital Integrated Circuits2nd,
