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1、CDC introductionFEINT TeamLillian Wei,June 16,2011,Outline,CDC Introduction,CDC Basic Concept FEINT CDC Overview FEINT CDC Debug Tile Flow Fullchip Flow Suggestion for future project,CDC Introduction,3,CDC Basic Concept,Overview,CDC Introduction,what is cdc?,Cdc:clock domain crossing.It is defined a
2、s a flop-to-flop path where transmitting flop is triggered by a clock that is asynchronous to the receiving flop clock.,Overview,CDC Introduction,Overview,CDC Introduction,metastability,Overview,CDC Introduction,How to protect against the post-silicon failures produced by cdc?,Designers should take
3、cdc issues seriously and use valid cdc scheme in hardware design stage;Efficient verification scheme should be used to double check cdc holes in design.our job,Spyglass cdc by Atrenta(before 9xx)0in cdc by Mentor,CDC Introduction,8,FEINT CDC Overview,FEINT CDC Overview,CDC Introduction,As we have LE
4、C,cdc life is easier;whats more,design period is shorter:,FEINT CDC Overview(tile level flow),CDC Introduction,10,CDC Introduction,11,FEINT CDC Overview(tile level flow),setup.tcltemplate.tcltemplateZin3.tclgenerate.tclprocs.tcl,guts40incdc,“vf”File,Project Filesproject.tclconfig.tcl,UserCustomizati
5、on,Tool Run Script,Rpts+logs+hier ctrl file,User Inputs,Project Inputs,GUTS Infrastructure,Outputs,Libraries,RTL Files,0in Tool,$tile.run.bsub,$tile.run,$tile.run.tcl,FEINT CDC Overview(tile level flow),CDC Introduction,12,FEINT CDC Overview(chip level),CDC Introduction,13,CHIP,IO,CORE,CHIP,PAD,TILE
6、,FEINT CDC Overview(chip level),CDC Introduction,14,If there is no info for the pad then 0in will report a blackbox crossingDefault for the flow to generate and use control files for all pads,but this causes noise in the runsChanging to a user defined list in the future,chip,core,io,tile,Pad(macro),
7、FEINT CDC Overview(chip level flow),CDC Introduction,15,CDC Introduction,16,FEINT CDC Debug,Debug Steps:,Resolve inferred clocks Clean warnings Clean violations,GUTS New User Training,17,Step 1:Resolve inferred clocks.(tile/chip),Look into$cdcwrkdir/$tile_cdc_output/0in_cdc_design.rpt,search“Inferre
8、d Clock Groups”,if the num is not 0,refine the clock defination in ctrl file and rerun cdc till no inferred clk:Clock Group Summary for ds_t=Total Number of Clock Groups:3Number of User-Defined Clock Groups:3Number of Inferred Clock Groups:0Number of Ignored Clock Groups:0,CDC Introduction,18,Step 2
9、:Clean important warnings.(tile),Look into$cdcwrkdir/$tile_cdc_output/0in_detail.log,search below warnings and clean them:Warning:netlist-44 Incomplete input/output specifications for the blocks inside top module.Warning:netlist-78 Tile input port is unusedWarning:netlist-79 Tile output port is undr
10、ivenWarning:netlist-80 Tile port clock domain cannot be inferred(We should expect 0 netlist-80 warning to generate good Hier control File),CDC Introduction,19,More info:http:/sharedbook/twiki/bin/view/Capeverde/TileLevelCDC_warning_review_update,Warning:netlist-44 Incomplete input/output specificati
11、ons for the blocks inside top module.,CDC Introduction,20,sub-block,DFF,Top module,The output port of the sub-block is not defined,tool will skip the cdc check for it.,clk_a,Step 2:Clean important warnings.(tile),Step 2:Clean important warnings.(tile),Warning:netlist-78 Tile input port is unusedInpu
12、t port of a hierarchical CDC block is not used by the block.Port is marked with the-ignore flag in the CFM.Check that the port is truly unused.Cases:Really unused intently or reserved for later step(scan logic);Seems used,but really not used for special logic:mux,and.,CDC Introduction,21,Step 2:Clea
13、n important warnings.(tile),Warning:netlist-79 Tile output port is undriven.Output port of a hierarchical CDC block is not driven in the block.Port is marked with the-ignore flag in the CFM.Check that the port is truly undriven.If the port should be part of a clock domain,add a set_cdc_port_domain d
14、irective for the port to the hierarchical constraints file for the block.Case:1)Really undriven(covered in designProblem.waiver);2)Driven by encrypt module,CDC Introduction,22,Step 2:Clean important warnings.(tile),Warning:netlist-80 Tile ports clock domain cannot be inferred.This warning is issued
15、for an input port if the port fans out to output ports using combinational logic(not sequential logic).If you specify the-combo_path option to the set_cdc_port_domain directives for the output ports and the input ports are listed,then you can ignore this message.,CDC Introduction,23,Step 2:Clean imp
16、ortant warnings.(chip),CDC Introduction,24,Warning:netlist-44Incomplete input/output specifications for port.Warning:netlist-56Tile clock constraint violated.Warning:netlist-58Tile port not defined as a clock in block control file.Warning:netlist-61Tile clock not connected to a clock at top level.Be
17、low two types are not found in verde:Warning:netlist-60Block port is not a constant.Warning:netlist-70Inconsistent constant values at block and top level.More info:http:/,Step 3:Clean important violations.(tile),most common violation types:1)no_sync 2)multi_bits 3)combo_logic 4)redundant 5)black_box
18、-which need to waive?-which need to fix?,CDC Introduction,25,-tile violation debug,no_sync:Single-bit signal does not have proper synchronizer,CDC Introduction,26,-tile violation debug,violation example:no_sync,CDC Introduction,27,no_sync:CLK P1500_TCLK,FROM vl_sms_bf_t_sms_proc_sms_1_stp.U_bf_t_sms
19、_proc_ieee1500.sms_si-CLK SCLK,TO vl_sms_bf_t_sms_proc_sms_1_stp.U_bf_t_sms_proc_ctrl.status_r0(ID:no_sync_91489),-tile violation debug,multi_bits:Multiple-bit signal across clock domain boundary.,CDC Introduction,28,-tile violation debug,violation example:multi_bits,CDC Introduction,29,multi_bits:C
20、LK P1500_TCLK,FROM vl_sms_ds_t_sms_proc_sms_1_stp.U_ds_t_sms_proc_ieee1500.wir_r-CLK SCLK,TO vl_sms_ds_t_sms_proc_sms_1_stp.U_ds_t_sms_proc_met.m_instr(ID:multi_bits_494),-tile violation debug,combo_logic:Combinational logic before synchronizer.,CDC Introduction,30,-tile violation debug,violation ex
21、ample:Combinational logic before synchronizer.,CDC Introduction,31,combo_logic:CLK SCLK,FROM pgfsm.pgfsm_cntl_reg6-CLK DCLK,TO uvdm.uvdm_core.uvd_rst_sync.rst_combine_dclk.sync_hard.sync_r.D(ID:combo_logic_24638),-tile violation debug,redundant:Redundant synchronization.,CDC Introduction,32,-tile vi
22、olation debug,violation example:redundant.,CDC Introduction,33,-tile violation debug,blackbox:Crossing drives an instance of an inferred black box.,CDC Introduction,34,-tile violation debug,violation example:blackbox.,CDC Introduction,35,Note:for blackbox violations,a good way to fix is set black_bo
23、x for the sub-block,and set port domain for the IO ports of the sub-block if they need to check cdc.,blackbox:CLK SCLK,FROM tmonw0.THM_TMON_tmon_bgadj_ff2-CLK,TO tmonw0.utmons.utmon.TMON_BGADJ2(ID:blackbox_18164),-tile violation debug,Cases of clock N/A in the violation rpt:Tile primary input port:a
24、)connected to different clock domain registers;-tile level miss crossing check,CDC Introduction,36,-tile violation debug,b)defined as“async”in the ctrl file;default is not async,see$tile_cdc_output/0in_detail.log:Global CDC Preference-Option Value-input_async FALSE if need change it,set/0in set_cdc_
25、preference-input_async,CDC Introduction,37,-tile violation debug,2)From bboxs output;3)Connect to the“D”pin of a sync cell(due to define-async for the sync cells D pin),CDC Introduction,38,Step 3:Clean important violations.(chip),most common violation types:1)black_box 2)combo_logic 3)multi_bits 4)n
26、o_sync,CDC Introduction,39,-chip violation debug,violation example:blackbox.,CDC Introduction,40,Note:for blackbox violations,indeed it is a tool bug,as all modules is CFM model or been set as blackbox,so no blackbox issue is expected.Here the blackbox violations are all good crossing.,#Waived:John
27、Wortman.#Reason:These are okey to waive since there is the sync cell in the reciever side.#Date:03/03/2011.#Comments:Good crossing,tool issue.cdc0in WAIVE Johnw chip blackbox CLK SCLK,FROM core.ct_t.SMU_MC_misc_vbi.*-CLK MCLK,TO core.mcd_t0|1.SMU_MC_misc_vbi,/0in set_cdc_port_domain SMU_MC_misc_vbi-
28、clock cg_tile_gbl_sclk-module ct_t/0in set_cdc_port_domain SMU_MC_misc_vbi-async-clock IO_MCD_chp_mclk_src-module mcd_t,Violation:blackbox:CLK SCLK,FROM core.ct_t.SMU_MC_misc_vbi-CLK MCLK,TO core.mcd_t0.SMU_MC_misc_vbi,-chip violation debug,violation example:combo_logic.,CDC Introduction,41,combo_lo
29、gic:CLK,FROM core.ct_t.SMU_SQ_power_throttle_cycle_incr-CLK SCLK,TO core.sqc_000.SMU_SQ_power_throttle_cycle_incr(ID:combo_logic_66295),Hier ctrl file:/0in set_cdc_port_domain SMU_SQ_power_throttle_cycle_incr-clock cg_tile_gbl_sclk-combo_path IO_TARG_io_resetb IO_CG_xtalin_clk BIF_CG_bclk_src cts_de
30、lay_csel cts_delay_cbypass cg_tile_gbl_sclk-module ct_t-combo_logic/0in set_cdc_port_domain SMU_SQ_power_throttle_cycle_incr-async-clock cg_gbl_sclk-module sqc0_t,-chip violation debug,violation example:combo_logic.,CDC Introduction,42,-chip violation debug,violation example:combo_logic.,CDC Introdu
31、ction,43,#Waived:Mihir Doctor#Reason:No glitch on the combo_logic.#Date:03/06/2011#Comments:Although the endpoint is synced to SCLK domain,the startpoint(from ct_t tile)is faned out from combo_logic,and the combo_logics input is from different clock domains(SCLK,BCLK,XCLK),so we could see a combo_lo
32、gic issue in the rpt.#Mihir:This is fine to waive.Muxes you showed do not switch dynamically.We set them once at bootup and do not change afterwards.cdc0in WAIVE liwei chip combo_logic CLK,FROM core.ct_t.SMU_SQ_power_throttle_cycle_incr.*-CLK SCLK,TO core.sqc_0(00|01|10|11).SMU_SQ_power_throttle_cyc
33、le_incr,Note:suggestion on such case is flip-flop out each primary output for all tiles.,-chip violation debug,violation example:multi_bits.,CDC Introduction,44,multi_bits:CLK,FROM core.cpl_efuse_t.IO_RCU_efuse0_q-CLK ZCLK,TO core.ct_t.IO_RCU_efuse0_q(ID:multi_bits_85164),Hier ctrl file:/0in set_cdc
34、_port_domain IO_RCU_efuse0_q-clock smu.clk.clk_mon_divide.d0nt_SDC_set_false_path_to_zclk.Y-module ct_t/0in set_cdc_clock smu.clk.clk_mon_divide.d0nt_SDC_set_false_path_to_zclk.Y-module ct_t-virtual-group ZCLK,#Waived:Jeffrey Zhang#Reason:the IO_RCU_efuse0_*is semi-static,programed once and never ch
35、ange,so surely not let the destination flop going metastable.#Date:02/11/2011#Comments:CLK is because no defination for ports of cpl_efuse_ts macro EFUSE_128x32_LS_OVLB1.cdc0in WAIVE jefzhang chip multi_bits CLK,FROM core.cpl_efuse_t.IO_RCU_efuse0_q.*-CLK ZCLK,TO core.ct_t.IO_RCU_efuse0_q,-chip viol
36、ation debug,violation example:multi_bits.,CDC Introduction,45,-chip violation debug,violation example:no_sync.,CDC Introduction,46,no_sync:CLK SCLK,FROM core.gdc_t.RCU_GDC_BIF_cec_hard_resetb-CLK,TO core.bf_t.RCU_GDC_BIF_cec_hard_resetb(ID:no_sync_70046),Hier ctrl file:/0in set_cdc_port_domain RCU_B
37、IF_cec_hard_resetb-clock cg_tile_gbl_sclk-module ct_t-combo_logic/0in set_cdc_port_domain RCU_GDC_BIF_cec_hard_resetb-combo_path RCU_BIF_cec_hard_resetb-module gdc_t/0in set_cdc_port_domain RCU_GDC_BIF_cec_hard_resetb-nosync-module bf_t-combo_logic,-chip violation debug,violation example:no_sync.,CD
38、C Introduction,47,/0in set_cdc_port_domain RCU_BIF_cec_hard_resetb-clock cg_tile_gbl_sclk-module ct_t-combo_logicct_t_rcu_reset.v:wire pre_RCU_CEC_chip_resetb=scan_mode?io_resetb:dglitch_rstb,-chip violation debug,violation example:no_sync.,CDC Introduction,48,/0in set_cdc_port_domain RCU_GDC_BIF_ce
39、c_hard_resetb-nosync-module bf_t-combo_logic,#Waived:aqin#Reason:These incoming signals are synchronized before use.#Date:04/13/2011#Comments:is because RCU_GDC_BIF_cec_hard_resetb goes to both sync cell and debug bus with combo logic.#due to tool limitation,hide a combo_logic issue here,RCU_BIF_cec
40、_hard_resetb goes out from ct_t with combo_logic,through gdc_t,then feed into bf_t,Viney confirmed its glitch free out of ct_t(see mail 2011/04/15),so safe to waive.ct_t_rcu_reset.v:wire pre_RCU_CEC_chip_resetb=scan_mode?io_resetb:dglitch_rstb cdc0in WAIVE aqin chip no_sync CLK SCLK,FROM core.gdc_t.
41、RCU_GDC_BIF_cec_hard_resetb.*-CLK,TO core.bf_t.RCU_GDC_BIF_cec_hard_resetb,-chip violation debug,violation example:no_sync.,CDC Introduction,49,CDC Introduction,50,Tile level CDC Flow,Tile level CDC Flow,Will cover:-prepare input files-how to run-what have been done in the run-flow output files,CDC
42、Introduction,51,Tile level CDC Flow,-prepare input files-how to run-what have been done in the run-flow output files,CDC Introduction,52,Tile level CDC Flow,flow input files:1)rtl code:generated by“runTileFlow.csh t$tile step sms”$STEM/main/auto/verde_amd64rh3.0_dbg/src/tiles/tile/$tile/sms_rtl/,CDC
43、 Introduction,53,Tile level CDC Flow,flow input files:2)sdc file:generated by“runTileFlow.csh t$tile step gensdc4cdc”$STEM/main/nl/wrk/variant/verde/$tile/sdc/CDC/$tile.sdcThe sdc file is used as a starting point for the constraints:,CDC Introduction,54,Tile level CDC Flow,flow input files:3)Ctrl fi
44、les:manually typed,set some constraints for cdc analysis,just like clock group of the clock or port,blackbox,custom sync cell(more later)global:$STEM/main/cmn/tools/guts/variant/verde/project.0in_ctrl.v tile level:$STEM/main/nl/setup/variant/verde/tile/$tile/$tile.0in_ctrl.v base ctrl file(provide/m
45、aintain by CAD Team):$STEM/main/cmn/tools/guts/bin/cdc0in/guts0incdc_base_ctrl.v,CDC Introduction,55,Tile level CDC Flow,-prepare input files-how to run-what have been done in the run-flow output files,CDC Introduction,56,Tile level CDC Flow,how to run:runTileFlow.csh t$tile step cdc0in call guts40i
46、ncdc script gen$tile.run.tcl(include 0in run cmd),CDC Introduction,57,Tile level CDC Flow,config tool version:0in/3.0c-p1,CDC Introduction,58,This variable is set each time opening a new shell,$STEM/main/setup/scripts/init/modules/fe_versions/variant/$PROJECT/default:#0insetenv GPG_0IN_VERSION 3.0c-
47、p1,Tile level CDC Flow,Then GPG_0IN_VERSION is used in$STEM/cmn/tools/guts/variant/$PROJECT/config.tcl:if$TARGET=cdc0in set config(toolVersion)0in/$env(GPG_0IN_VERSION)regexp 0in/(d+).$config(toolVersion)match cdcVersion if$cdcVersion=2 set config(templateScr)$config(toolRoot)/cdc0in/template.tcl el
48、seif$cdcVersion=3 set config(templateScr)$config(toolRoot)/cdc0in/templateZin3.tcl Note:Do not use“module load”to choose tool version,what really used by 0in flow is decide by“toolVersion”.,CDC Introduction,59,Tile level CDC Flow,CDC Introduction,60,0in cdc-report_settings-d$tile hier-ctrl$STEM/main
49、/cmn/tools/guts/bin/cdc0in/guts0incdc_base_ctrl.v-ctrl$STEM/main/cmn/tools/guts/variant/verde/project.0in_ctrl.v-ctrl$STEM/main/nl/setup/variant/verde/tile/$tile/$tile.0in_ctrl.v-formal-formal_effort low-process_dead_end-sdc_in$STEM/main/nl/wrk/variant/verde/$tile/sdc/CDC/$tile.sdc,0in run cmd:,Tile
50、 level CDC Flow,-prepare input files-how to run-what have been done in the run-flow output files,CDC Introduction,61,Tile level CDC Flow,what have been done in the run:,CDC Introduction,62,Works on RTL source code,analysis the design Automatically identifies all clocks and clock domain crossings Aut
