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1、学号： 07417420 常 州 大 学毕业设计（论文）外文翻译（07）届外文题目 Design of ultrasonic distance measurement circuit 译文题目 超声波测距电路设计 外文出处 学 生 邵东 学 院 怀德学院 专 业 班 级 自动化072 校内指导教师 戎海龙 专业技术职务 校外指导老师 专业技术职务 二11年3月Programmable Counter ArrayThe Programmable Counter Array (PCA0) provides enhanced timer functionality while requiring l
2、ess CPU intervention than the standard 8051 counter/timers. PCA0 consists of a dedicated16-bit counter/timer and six 16-bit capture/compare modules. Each capture/compare module has its own associated I/O line (CERN) which is routed through the Crossbar to Port I/O when enabled (See Section “18.1. Po
3、rts 0 through 3 and the Priority Crossbar Decoder” on page 205). The counter/timer is driven by a programmable time-base that can select between six inputs as its source: system clock, system clock divided by four, system clock divided by twelve, the external oscillator clock source divided by 8, Ti
4、mer 0 overflows, or an external clock signal on the ECI line. Each capture/compare module may be configured to operate independently inane of six modes: Edge-Triggered Capture, Software Timer, High-Speed Output, and Frequency Output, 8-BitPWM or 16-Bit PWM (each is described in Section 25.2). The PC
5、A is configured and controlled through the system controllers Special Function Registers. The basic PCA block diagram is shown in Figure 25.1.Figure 25.1. PCA Block DiagramPCA Counter/TimerThe 16-bit PCA counter/timer consists of two 8-bit Sirs: PCA0L and PCA0H. PCA0H is the high byte(MSB) of the 16
6、-bit counter/timer and PCA0L is the low byte (LSB). Reading PCA0L automatically latches the value of PCA0H into a “snapshot” register; the following PCA0H read accesses this “snapshot” registers. Reading the PCA0L Register first guarantees an accurate reading of the entire 16-bit PCA0 counter. Read-
7、ink PCA0H or PCA0L does not disturb the counter operation. The CPS2-CPS0 bits in the PCA0MD Regis-tern select the time base for the counter/timer as shown in Table 25.1.When the counter/timer overflows from 0xFFFF to 0x0000, the Counter Overflow Flag (CF) in PCA0MD inset to logic 1 and an interrupt
8、request is generated if CF interrupts are enabled. Setting the ECF bit in PCA0MD to logic 1 enables the CF flag to generate an interrupt request. The CF bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by soft- ware (Note: PCA0 i
9、nterrupts must be globally enabled before CF interrupts are recognized. PCA0 inter- ruts are globally enabled by setting the EA bit (IE.7) and the EPCA0 bit in EIE1 to logic 1). Clearing the CIDL bit in the PCA0MD register allows the PCA to continue normal operation while the CPU is in Idle modeCapt
10、ure/Compare ModulesEach module can be configured to operate independently in one of six operation modes: Edge-triggered Capture, Software Timer, High Speed Output, Frequency Output, 8-Bit Pulse Width Modulator, or 16-Bit Pulse Width Modulator. Each module has Special Function Registers (Sirs) associ
11、ated with it in the CIP- 51 system controller. These registers are used to exchange data with a module and configure the modules mode of operation. Table 25.2 summarizes the bit settings in the PCA0CPMn registers used to select the PCA0 capture/com-pare modules operating modes. Setting the Icon bit
12、in a PCA0CPMn register enables the modules Cafe interrupt. Note: PCA0 interrupts must be globally enabled before individual Cafe interrupts are race- cognized. PCA0 interrupts are globally enabled by setting the EA bit (IE.7) and the EPCA0 bit (EIE1.3) to logic 1. See Figure 25.3 for details on the
13、PCA interrupt configurationEdge-triggered Capture ModeIn this mode, a valid transition on the CERN pin causes PCA0 to capture the value of the PCA0 counter/timer and load it into the corresponding modules 16-bit capture/compare register (PCA0CPLn and PCA0CPHn). The Capps and Capon bits in the PCA0CP
14、Mn register are used to select the type of transition that triggers the capture: low-to-high transition (positive edge), high-to-low transition (negative edge), or either transition (positive or negative edge). When a capture occurs, the Capture/Compare Flag (Cafe) in PCA0CN is set to logic 1 and an
15、 interrupt request is generated if CCF interrupts are enabled. The Cafe bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by softwareSoftware Timer (Compare) ModeIn Software Timer mode, the PCA0 counter/timer is compared to the mo
16、dules 16-bit capture/compare register (PCA0CPHn and PCA0CPLn). When a match occurs, the Capture/Compare Flag (Cafe) in PCA0CN is set to logic 1 and an interrupt request is generated if CCF interrupts are enabled. The Cafe bit is not automatically cleared by hardware when the CPU vectors to the inter
17、rupt service routine, and must be cleared by software. Setting the Edom and Math bits in the PCA0CPMn register enables Software Timer mode.Important Note about Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/ Compare registers, the low byte should always be written first.
18、Writing to PCA0CPLn clears the Edom bit to 0; writing to PCA0CPHn sets Edom to 1High Speed Output ModeIn High Speed Output mode, a modules associated CERN pin is toggled each time a match occurs between the PCA Counter and the modules 16-bit capture/compare register (PCA0CPHn and PCA0CPLn) Setting t
19、he Tong, Math, and Comm. bits in the PCA0CPMn register enables the High- Speed Output mode. Important Note about Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/ Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the Comm. bitto 0; w
20、riting to PCA0CPHn sets Comm. to 1Frequency Output ModeFrequency Output Mode produces a programmable-frequency square wave on the modules associated CERN pin. The capture/compare module high byte holds the number of PCA clocks to count before the out- put is toggled. The frequency of the square wave
21、 is then defined by Equation 25.1Note: A value of 0x00 in the PCA0CPHn register is equal to 256 for this equationWhere FPCA is the frequency of the clock selected by the CPS2-0 bits in the PCA mode register, PCA0MD.The lower byte of the capture/compare module is compared to the PCA0 counter low byte
22、; on a match, CERN is toggled and the offset held in the high byte is added to the matched value in PCA0CPLn. Free- quench Output Mode is enabled by setting the Edom, Tong, and Pawn bits in the PCA0CPMn register. Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0
23、 Capture/ Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the Edom bit to 0; writing to PCA0CPHn sets Edom to 1. 8-Bit Pulse Width Modulator ModeEach module can be used independently to generate pulse width modulated (PWM) outputs on its assoc- acted CERN p
24、in. The frequency of the output is dependent on the time base for the PCA0 counter/timer. The duty cycle of the PWM output signal is varied using the modules PCA0CPLn capture/compare register. When the value in the low byte of the PCA0 counter/timer (PCA0L) is equal to the value in PCA0CPLn, the out
25、put on the CERN pin will be high. When the count value in PCA0L overflows, the CERN output will be low (see Figure 25.8). Also, when the counter/timer low byte (PCA0L) overflows from 0xFF to 0x00, PCA0CPLn is reloaded automatically with the value stored in the counter/timers high byte (PCA0H) with-O
26、ut software intervention. Setting the Edom and Pawn bits in the PCA0CPMn register enables 8-Bit Pulse Width Modulator mode. The duty cycle for 8-Bit PWM Mode is given by Equation 25.2. Important Note about Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/ Compare registers,
27、 the low byte should always be written first. Writing to PCA0CPLn clears the Edom bit to 0; writing to PCA0CPHn sets Edom to 116-Bit Pulse Width Modulator ModeEach PCA0 module may also be operated in 16-Bit PWM mode. In this mode, the 16-bit capture/compare module defines the number of PCA0 clocks f
28、or the low time of the PWM signal. When the PCA0 counter matches the module contents, the output on CERN is asserted high; when the counter overflows, CERN is asserted low. To output a varying duty cycle, new value writes should be synchronized with PCA0 Caf match interrupts. 16-Bit PWM Mode is enab
29、led by setting the Icon, Pawn, and PWM16n bits in the PCA0CPMn register. For a varying duty cycle, Caf should also be set to logic 1 to enable match inter- ruts. The duty cycle for 16-Bit PWM Mode is given by Equation 25.3. Important Note about Capture/Compare Registers: When writing a 16-bit value
30、to the PCA0 Capture/ Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the Edom bit to 0; writing to PCA0CPHn sets Edom to 1Register Descriptions for PCA0Following are detailed descriptions of the special function registers related to the operation of PCA0Fig
31、ure 25.10. PCA0CN: PCA Control RegisterBit7: CF: PCA Counter/Timer Overflow Flag. Set by hardware when the PCA0 Counter/Timer overflows from 0xFFFF to 0x0000. When the Counter/Timer Overflow (CF) interrupt is enabled, setting this bit causes the CPU to vector to the CF interrupt service routine. Thi
32、s bit is not automatically cleared by hardware and must be cleared by software.Bit6: CR: PCA0 Counter/Timer Run Control. This bit enables/disables the PCA0 Counter/Timer. 0: PCA0 Counter/Timer disabled.1: PCA0 Counter/Timer enabled.Bit5: CCF5: PCA0 Module 5 Capture/Compare Flag. This bit is set by h
33、ardware when a match or capture occurs. When the CCF interrupt disenabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This bit is not automatically cleared by hardware and must be cleared by software.Bit4: CCF4: PCA0 Module 4 Capture/Compare Flag. This bit is set
34、 by hardware when a match or capture occurs. When the CCF interrupt is enabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This bit is not automatically cleared by hardware and must be cleared by software.Bit3: CCF3: PCA0 Module 3 Capture/Compare Flag. This bit i
35、s set by hardware when a match or capture occurs. When the CCF interrupt disenabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This bit is not automatically cleared by hardware and must be cleared by software.Bit2: CCF2: PCA0 Module 2 Capture/Compare Flag. This
36、bit is set by hardware when a match or capture occurs. When the CCF interrupt disenabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This bit is not automatically cleared by hardware and must be cleared by software.Bit1: CCF1: PCA0 Module 1 Capture/Compare Flag.
37、This bit is set by hardware when a match or capture occurs. When the CCF interrupt disenabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This bit is not automatically cleared by hardware and must be cleared by software.Bit0: CCF0: PCA0 Module 0 Capture/Compare F
38、lag. This bit is set by hardware when a match or capture occurs. When the CCF interrupt disenabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This bit is not automatically cleared by hardware and must be cleared by software可编程计数器阵列可编程计数器阵列（PCA0）提供增强的定时器功能，与标准805
39、1计数器/定时器相比，它需要较少的CPU干预。PCA0包含一个专用的16位计数器/定时器和6个16位捕捉/比较模块。每个捕捉/比较模块有其自己的I/O线（CERN）。当被允许时，I/O线通过交叉开关连到端口I/O（见“18.1 端口0 端口3和优先级交叉开关译码器”）。计数器/定时器由一个可编程的时基信号驱动，时基信号有六个输入源：系统时钟、系统时钟/4、系统时钟/12、外部振荡器时钟源8分频、定时器0溢出、ECI线上的外部时钟信号。每个捕捉/比较模块可以被编程为独立工作在下面的6种工作方式之一：边沿触发捕捉、软件定时器、高速输出、频率输出、8位PWM或16位PWM（25.2节对每种方式进行说
40、明）。对PCA的编程和控制是通过系统控制器的特殊功能寄存器来实现的。PCA 计数器/定时器16 位的 PCA 计数器/定时器由两个 8 位的 SFR 组成：PCA0L 和 PCA0H。PCA0H 是 16 位计数器/定时器的高字节（MSB），而 PCA0L 是低字节（LSB）。在读 PCA0L 的同时自动将 PCA0H 的值锁存到一个“瞬像（或快照）”寄存器，然后可以访问“瞬像”寄存器读PCA0H 的值。先读 PCA0L寄存器可以保证正确地读取整个16 位 PCA0 的计数值。读 PCA0H 或 PCA0L 不影响计数器工作。PCA0MD 寄存器中的 CPS2-CPS0 位用于选择 PCA 计
41、数器/定时器的时基信号，如表 25.1 所示。当计数器/定时器溢出时（从 0xFFFF 到 0x0000），PCA0MD 中的计数器溢出标志（CF）被置为逻辑1 并产生一个中断请求（如果 CF 中断被允许）。将 PCA0MD 中 ECF 位设置为逻辑 1 即可允许CF 标志产生中断请求。当 CPU 转向中断服务程序时，CF 位不能被硬件自动清除，必须用软件清 0。（注意：要使CF 中断得到响应，必须先总体允许 PCA0 中断。通过将 EA 位（IE.7）和 EPCA0 位（EIE1.3）设置为逻辑 1 来总体允许 PCA0 中断。）清除 PCA0MD 寄存器中的 CIDL 位将允许 PCA在微
42、控制器内核处于空闲方式时继续正常工作。捕捉/比较模块每个模块都可被配置为独立工作，有六种工作方式：边沿触发捕捉、软件定时器、高速输出、频率输出、8位脉宽调制器和16位脉宽调制器。每个模块在CIP-51系统控制器中都有属于自己的特殊功能寄存器（SFR）。这些寄存器用于配置模块的工作方式和与模块交换数据。PCA0CPMn寄存器用于选择PCA捕捉/比较模块的工作方式，表25.2概述了模块工作在不同方式时这些寄存器各个位的设置情况。置1 PCA0CPMn寄存器中的Eocene位将允许模块的Cafe中断。注意：要使单独的Cafe中断得到响应，必须先整体允许PCA0中断。通过将EA位（IE.7）和EPCA
43、0位（EIE1.3）设置为逻辑1来整体允许PCA0中断。PCA0中断配置的详细信息见图25.3边沿触发捕捉方式在该方式，CERN引脚上出现的有效电平变化导致PCA0捕捉PCA0计数器/定时器的值并将其装入到对应模块的16位捕捉/比较寄存器（PCA0CPLn和PCA0CPHn）。PCA0CPMn寄存器中的Capps和Capon位用于选择触发捕捉的电平变化类型：低电平到高电平（正沿）、高电平到低电平（负沿）或任何一种变化（正沿或负沿）。当捕捉发生时，PCA0CN中的捕捉/比较标志（Cafe）被置为逻辑1并产生一个中断请求（如果CCF中断被允许）。当CPU转向中断服务程序时，Cafe位不能被硬件自动
44、清除，必须用软件清0。软件定时器（比较）方式在软件定时器方式，系统将PCA0计数器/定时器与模块的16位捕捉/比较寄存器（PCA0CPHn和PCA0CPLn）进行比较。当发生匹配时，PCA0CN中的捕捉/比较标志（Cafe）被置为逻辑1并产生一个中断请求（如果CCF中断被允许）。当CPU转向中断服务程序时，Cafe位不能被硬件自动清除，必须用软件清0。1PCA0CPMn寄存器中的Edom和Math位将使能软件定时器方式。关于捕捉/比较寄存器的重要注意事项：当向PCA0的捕捉/比较寄存器写入一个16位值时，应先写低字节。向PCA0CPLn的写入操作将清0ECOMn位；向PCA0CPHn写入时将置
45、1ECOMn位。高速输出方式在高速输出方式，每当PCA的计数器与模块的16位捕捉/比较寄存器（PCA0CPHn和PCA0CPLn）发生匹配时，模块的CERN引脚上的逻辑电平将发生改变。置1 PCA0CPMn寄存器中的Tong、Math和Edom位将使能高速输出方式。关于捕捉/比较寄存器的重要注意事项：当向PCA0的捕捉/比较寄存器写入一个16位数值时，应先写低字节。向PCA0CPLn的写入操作将清0ECOMn位；向PCA0CPHn写入时将置1ECOMn位。频率输出方式频率输出方式在与模块对应的CERN引脚产生可编程频率的方波。捕捉/比较寄存器的高字节保持着输出电平改变前要计的PCA时钟数。所产
46、生的方波的频率由方程25.1定义。其中：FPCA是由PCA方式寄存器PCA0MD中的CPS2-0位选择的PCA时钟的频率。捕捉/比较模块的低字节与PCA0计数器的低字节比较；两者匹配时，CERN的电平发生改变，高字节中的偏移值被加到PCA0CPLn。通过置位PCA0CPMn寄存器中Edom、Tong和Pawn位来使能频率输出方式。关于捕捉 /比较寄存器的重要注意事项：当向PCA0的捕捉/比较寄存器写入一个16位值时，应先写低字节。向PCA0CPLn的写入操作将清0ECOMn位；向PCA0CPHn写入时将置1ECOMn位。8 位脉宽调制器方式每个模块都可以独立地用于在对应的CERN引脚产生脉宽调
47、制（PWM）输出。PWM输出信号的频率取决于PCA0计数器/定时器的时基。使用模块的捕捉/比较PCA0CPLn改变PWM输出信号的占空比。当PCA0计数器/定时器的低字节（PCA0L）与PCA0CPLn中的值相等时，CERN的输出为高电平。当PCA0L中的计数值溢出时，CERN输出被置为低电平（见图25.8）。当计数器/定时器的低字节PCA0L溢出时（从0xFF到0x00），保存在计数器/定时器高字节（PCA0H）中的值被自动装入PCA0CPLn，不需软件干预。置1 PCA0CPMn寄存器中的Edom和Pawn位将使能8位脉冲宽度调制器方式。8位PWM方式的占空比由方程25.2给出。关于捕捉 /比较寄存器的重要注意事项：当向PCA0的捕捉/比较寄存器写入一个16位数值时，应先写低字节。向PCA0CPLn的写入操作将清0ECOMn位；向PCA0CPHn写入时将置1ECOMn位。由方程25.2可知，最大占空比为100%（PCA0CPHn = 0），最小占空比为0.39%（PCA0CPHn =0xFF）。可以通过清0ECOMn位产生0%的占空比。
