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1、VHDL程序设计题四、 编程题（共50分）1、请补全以下二选一VHDL程序（本题10分）Entity mux isport(d0,d1,sel:in bit;q:out BIT ); (2)end mux;architecture connect of MUX is (4) signal tmp1, TMP2 ,tmp3:bit; (6)begin cale:block begin tmp1=d0 and sel; tmp2=d1 and (not sel) tmp3= tmp1 and tmp2;q = tmp3; (8) end block cale; end CONNECT ; (10)
2、2、编写一个2输入与门的VHDL程序，请写出库、程序包、实体、构造体相关语句，将端口定义为标准逻辑型数据结构（本题10分）&abyLIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; （2） ENTITY nand2 IS PORT (a，b:IN STD_LOGIC; （4） y:OUT STD_LOGIC); （6） END nand2; ARCHITECTURE nand2_1 OF nand2 IS （8） BEGIN y = a NAND b; -与y =NOT( a AND b);等价 （10） END nand2_1;3、根据下表填写完成一个3-8
3、线译码器的VHDL程序（16分）。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY decoder_3_to_8 IS PORT (a,b,c,g1,g2a,g2b:IN STD_LOGIC; y:OUT STD_LOGIC_VECTOR(7 DOWNTO 0); （2）END decoder_3_to_8;ARCHITECTURE rtl OF decoder_3_to_8 IS SIGNAL indata:STD_LOGIC_VECTOR (2 DOWNTO 0);（4）BEGIN indata y y y y y y y y y = XXXX
4、XXXX; END CASE; ELSE y = 11111111;（14） END IF; END PROCESS;（16）END rtl; 4、三态门电原理图如右图所示，真值表如左图所示，请完成其VHDL程序构造体部分。（本题14分）LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;ENTITY tri_gate ISPORT(din,en:IN STD_LOGIC; dout : OUT STD_LOGIC);END tri_gate ;ARCHITECTURE zas OF tri_gate ISBEGIN PROCESS (din,en) BEGIN
5、IF (en=1) THEN dout = din;ELSE dout = Z; END IF; END PROCESS ;END zas ;四、 编程题（共50分）1、根据一下四选一程序的结构体部分，完成实体程序部分（本题8分）entity MUX4 is port( (2)s:in std_logic_vector(1 downto 0); (4)d:in std_logic_vector(3 downto 0); (6)y:out std_logic (8); end MUX4; architecture behave of MUX4 isbeginprocess(s)beginif (
6、s=00) theny=d(0); elsif (s=01) theny=d(1); elsif (s=10) theny=d(2); elsif (s=11) theny=d(3); elsenull; end if;end process;end behave; 2、编写一个数值比较器VHDL程序的进程（不必写整个结构框架），要求使能信号g低电平时比较器开始工作，输入信号p = q，输出equ为0，否则为1。（本题10分）process(p,q)(2)beginif g=0 then(4)if p = q thenequ = 0; (6)else equ = 1; (8)end if;el
7、se equ = 1; (10)end if;end process;3、填写完成一个8-3线编码器的VHDL程序（16分）。Library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity eight_tri is port(b:in std_logic_vector(7 downto 0); （2）en:in std_logic;y:outstd_logic_vector(2 downto 0) （4）);end eight_tri;arc
8、hitecture a of eight_tri is （6）signal sel: std_logic_vector(8 downto 0);beginsel=en & b; （8）y= “000” when (sel=”100000001”)else“001” when (sel=”100000010”)else （10）“010” when (sel=”100000100”)else“011” when (sel=”100001000”)else“100” when (sel=”100010000”)else （12） “101” when (sel=”100100000”)else“1
9、10” when (sel=”101000000”)else （14）“111” when (sel=”110000000”)else （16）“zzz”;end a;4、图中给出了4位逐位进位全加器，请完成其VHDL程序。（本题16分）library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_arith.all;use IEEE.std_logic_unsigned.all;entity full_add isport (a,b: instd_logic_vector (3 downto 0); （2）carr: inout st
10、d_logic_vector (4 downto 0);sum: outstd_logic_vector (3 downto 0);end full_add;architecture full_add_arch of full_add iscomponent adder （4）port (a,b,c:instd_logic;carr: inoutstd_logic;sum: out std_logic （6）);end component;begincarr(0)=0;u0:adder port map(a(0),b(0),carr(0),carr(1),sum(0);u1:adder por
11、t map(a(1),b(1),carr(1),carr(2),sum(1); （8）（10）u2:adder port map(a(2),b(2),carr(2),carr(3),sum(2); （12）u3:adder port map(a(3),b(3),carr(3),carr(4),sum(3); （14）（16）end full_add_arch;四、 编程（共50分）1、完成下图所示的触发器。（本题10分）CLRCLKDQQNlibrary IEEE;use IEEE.std_logic_1164.all;entity VposDff is port (CLK, CLR, D:
12、in STD_LOGIC; -2分 Q, QN: out STD_LOGIC ); -4分end VposDff;architecture VposDff_arch of VposDff isbegin process ( CLK, CLR ) -6分 begin if CLR=1 then Q = 0; QN =1; elsif CLKevent and CLK=1 then Q = D; QN = not D; -8分 end if; end process; -10分end VposDff_arch; 2、完成以下4位全加器代码（本题10分）library IEEE;use IEEE.s
13、td_logic_1164.all;entity full_add isport (a,b: instd_logic_vector (3 downto 0);cin: instd_logic;cout: out std_logic;sum: outstd_logic_vector (3 downto 0);end full_add;architecture full_add_arch of full_add iscomponent adderport (a,b,c:instd_logic;carr: outstd_logic;sum: out std_logic);end component;
14、signal c1,c2,c3: std_logic; 2分beginu0:adder port map(a(0),b(0),cin,c1,sum(0); 4分u1:adder port map(a(1),b(1),c1,c2,sum(1); 5分u2:adder port map(a(2),b(2),c2,c3,sum(2); 6分u3:adder port map(a(3),b(3),c3,cout,sum(3); 10分end full_add_arch;3、补充完整如下代码，使之完成4状态不断循环。(本题10分)ARCHITECTURE arc OF ss IStype states
15、is ( st0,st1,st2,st3 ); 2分signal outc: states; 4分BEGINPROCESS(clk) BEGIN IF reset=1 then outc outc outc outc outc outc =st0; END CASE; end if;END PROCESS;END arc; 4、设计异或门逻辑：（本题20分）如下异或门，填写右边的真值表。（此项5分）ABY000011101110其表达式可以表示为：（此项5分） 这一关系图示如下：试编写完整的VHDL代码实现以上逻辑。可以采用任何描述法。（此项10分）library ieee;use ieee.
16、std_logic_1164.all; 1分entity yihuo1 isport(a,b:in std_logic;y:out std_logic);end yihuo1; 4分architecture yihuo1_behavior of yihuo1 isbegin 7分process(a,b) y=a xor b;begin （第2种写法）if a=b theny=0;elsey=1;end if;end process; end yihuo1_behavior; 10分四、 编程（共50分，除特殊声明，实体可只写出PORT语句，结构体要写完整）1、用IF语句编写一个二选一电路，要求
17、输入a、b, sel为选择端，输出q。（本题10分）Entity sel2 isPort (a,b : in std_logic;sel : in std_logic;q : out std_logic);End sel2;(3)Architecture a of sel2 isbeginif sel = 0 thenq = a;(6)elseq = b;(9)end if;end a;(10)2、编写一个4位加法计数器VHDL程序的进程（不必写整个结构框架），要求复位信号reset低电平时计数器清零，变高后，在上升沿开始工作；输入时钟信号为clk，输出为q。（本题10分）Process(re
18、set,clk)(2)beginif reset = 0 thenq = “0000”;(4)elsif clkevent and clk = 1 then(6)q = q + 1;(9)end if;end process;(10)3、填写完成一个8-3线编码器的真值表（5分），并写出其VHDL程序（10分）。8 -3线编码器真值表enby0y1y21000000000001000000100011000001000101000010000111000100001001001000001011010000001101100000001110xxxxxxxx高阻态entity eight_tr
19、i is port(b:in std_logic_vector(7 downto 0);en:in std_logic;y:outstd_logic_vector(2 downto 0);end eight_tri;(3)architecture a of eight_tri is signal sel: std_logic_vector(8 downto 0);(4)beginsel=en & b;y= “000” when (sel=”100000001”)else“001” when (sel=”100000010”)else“010” when (sel=”100000100”)els
20、e“011” when (sel=”100001000”)else“100” when (sel=”100010000”)else“101” when (sel=”100100000”)else“110” when (sel=”101000000”)else“111” when (sel=”110000000”)else(9)“zzz”;(10)end a;4、根据已给出的全加器的VHDL程序，试写出一个4位逐位进位全加器的VHDL程序。（本题15分）library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_arith.all;us
21、e IEEE.std_logic_unsigned.all;entity adder isport (a,b,c:in std_logic;carr: inout std_logic;sum: out std_logic);end adder;architecture adder_arch of adder isbeginsum = a xor b xor c;carr = (a and b) or (b and c) or (a and c);end adder_arch;entity full_add isport (a,b: instd_logic_vector (3 downto 0)
22、;carr: inout std_logic_vector (4 downto 0);sum: outstd_logic_vector (3 downto 0);end full_add;(5)architecture full_add_arch of full_add iscomponent adderport (a,b,c:instd_logic;carr: inoutstd_logic;sum: out std_logic);end component;(10)begincarr(0)=0;u0:adder port map(a(0),b(0),carr(0),carr(1),sum(0
23、);u1:adder port map(a(1),b(1),carr(1),carr(2),sum(1);u2:adder port map(a(2),b(2),carr(2),carr(3),sum(2);u3:adder port map(a(3),b(3),carr(3),carr(4),sum(3);end full_add_arch;(15)四、 编程（共50分，除特殊声明，实体可只写出PORT语句，结构体要写完整）1、用IF语句编写一个四选一电路，要求输入d0d3, s为选择端，输出y。（本题10分）entity MUX4 is port(s:in std_logic_vector
24、(1 downto 0);d:in std_logic_vector(3 downto 0);y:out std_logic);end MUX4; (3)architecture behave of MUX4 isbeginprocess(s)beginif (s=00) theny=d(0); (4)elsif (s=01) theny=d(1); (5)elsif (s=10) theny=d(2); (6)elsif (s=11) theny=d(3); (7)elsenull; (9)end if;end process;end behave; (10)2、编写一个数值比较器VHDL程
25、序的进程（不必写整个结构框架），要求使能信号g低电平时比较器开始工作，输入信号p = q，输出equ为0，否则为1。（本题10分）process(p,q)(2)beginif g=0 then(4)if p = q thenequ_tmp = 0;(6)else equ_tmp = 1;(8)end if;else equ_tmp = 1;(10)end if;end process;3、填写完成一个3-8线译码器的真值表（5分），并写出其VHDL程序（10分）。3-8译码器的真值表ena2a1a0y10000000000110010000001010100000010010110000100
26、01100000100001101001000001110010000001111100000000xxx00000000entity tri_eight is port(a:in std_logic_vector (2 downto 0);en:in std_logic;y:outstd_logic_vector (7 downto 0);end tri_eight;(2)architecture a of tri_eight is signal sel:std_logic_vector (3 downto 0);(4)beginsel(0) = a(0);sel(1) = a(1);sel
27、(2) = a(2);sel(3) = en;(5)with sel selecty = 00000001 when 1000,00000010 when 1001,00000100 when1010,00001000 when1011,00010000 when1100,00100000 when1101,01000000 when1110,10000000 when1111,00000000 whenothers;(9)end a;(10)4、根据已给出的二-十（BCD）进制优先权编码器功能表，试写出其VHDL程序。（本题15分）二-十（BCD）进制优先权编码器功能表输入输出I1I2I3I
28、4I5I6I7I8I9Y3Y2Y1Y01111111111111XXXXXXXX00110XXXXXXX010111XXXXXX0111000XXXXX01111001XXXX011111010XXX0111111011XX01111111100X0111111111010111111111110entity prior isport(d : in std_logic_vector(9 downto 1);q : out std_logic_vector(3 downto 0);end prior;(2)architecture behavior of prior is beginproces
29、s(d)(4)beginif d = 111111111 thenq = 1111;elsif d(9) = 0 thenq = 0110;elsif d(8) = 0 thenq = 0111;elsif d(7) = 0 thenq = 1000;elsif d(6) = 0 thenq = 1001;elsif d(5) = 0 thenq = 1010;elsif d(4) = 0 thenq = 1011;elsif d(3) = 0 thenq = 1100;elsif d(2) = 0 thenq = 1101;elsif d(1) = 0 thenq = 1110;end if;(9)end process;end behavior;
