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1、timescale 1ns / 10 ps/Filename: AT24C02B_rev_F_2008/ AT24C Device Family/ Note: Compiler directives are used to adapt the model to a particular / device of the family./ Note: Choose VERBOSE 0 to suppress troubleshooting messages./ Dates of Revisions:/ m.d. ciletti 03/05/03/ m.d. ciletti 04/28/2006 /
2、 m.d. ciletti 05/30/2008/ B. Morgan 7/23/2008/ m.d. ciletti 7/26/2008/ Summary of Revisions/ Pre-2008 Modified to handle the following device functionality:/ (1) Detects toggling of SDA under SCL = 1 and cancels the START condition/ if the sequence ends with a STOP condition./ (2) Detects and recove
3、rs from a random START condition, i.e. if a start/ condition appears anywhere in the data transmission the machine resets / itself to begin receiving a device address byte./ (3) Detects a sequence of 9 clocks with SDA held high and resets the / machine to await a START condition. The address registe
4、r of the machine / is not affected by the reset operation./ (4) Corrects an occurrence of an incorrect device label for the / AT24C1024 device. / (5) Includes address code for the P bits (had been removed for testing) / 05/30/2008 Modified to deal with infinite loop upon time out for page / write./
5、05/30/2008 Modified to provide additional documentation./ 7/23/2008 Added 24C512B 1.8v 400khz and 2.5v 1Mhz timing sets./ 7/26/2008 Modified to handle protocol violation with WP (write protection)/ and provide additional documentation./ Required reset of Valid_Address_flag./ Corrected code entries f
6、or AT24C512B./ DEVICE SELECTION/define WANT_VERBOSE 1/ Slave address formats/1M1010_0_A1_P0_R/W/512K1010_0_A1_A0_R/W/256K1010_0_A1_A0_R/W/128K1010_0_A1_A0_R/W/64K1010_A2_A1_A0_R/W/32K1010_A2_A2_A0_R/W/16K1010_P1_P1_P0_R/W/8K1010_A2_P1_P0_R/W /4K1010_A2_A1_P0_R/W/2K1010_A2_A1_A0_R/W/1K1010_A2_A1_A0_R
7、/W/ To configure the model, edit the comments of the compiler / directives as specfifed below : / (1) remove / from the define line of the selected device (REQUIRED)/ (2) remove / to select timing parameters (OPTIONAL)/ (3) set the SLAVE_ADDRESS (REQUIRED)/ (Arbitrary addresses are used below for te
8、sting)/ Be sure that the test bench is adapted to the particular model/ No further action needed./define AT24C1024 /define AT24C512B/ define AT24C512/define AT24C256/define AT24C128/define AT24C64A/define AT24C32A/define AT24C16A/define AT24C08A/define AT24C04Adefine AT24C02A/define AT24C01A/define
9、AT24C64/define AT24C32/define AT24C08/define AT24C04/define AT24C02/define AT34C02/ Options for timing parameters/define WANT_AT24C1024_4_5_5_5V_TIMING/define WANT_AT24C1024_2_7_5_5V_TIMING/define WANT_AT24C_01A_02_04_08_16_2_7_2_5_1_8_VOLT_TIMINGdefine WANT_AT24C_01A_02_04_08_16_5_VOLT_TIMING/defin
10、e WANT_AT24C_02A_04A_08A_16A_1_8_V_TIMING/define WANT_AT24C_02A_04A_08A_2_5V_2_7V_TIMING/define WANT_AT24C_16A_2_5V_TIMING/define WANT_AT24C_02A_04A_08A_16A_5V_TIMING/define WANT_AT24C512B_1_8V_TIMING/define WANT_AT24C512B_2_5V_TIMING/define WANT_AT24C512_1_8_V_TIMING/define WANT_AT24C512_2_7V_TIMIN
11、G/define WANT_AT24C512_5V_TIMING/define WANT_AT24C128_256_1_8_V_TIMING/define WANT_AT24C128_256_2_5V_TIMING/define WANT_AT24C128_256_5V_TIMING/define WANT_AT34C02_1_8_VOLT_TIMING/define WANT_AT34C02_2_7_5_0_VOLT_TIMINGifdef AT24C1024 module AT24C1024 (SDA, SCL, WP);endififdef AT24C512B module AT24C5
12、12B (SDA, SCL, WP);endififdef AT24C512 module AT24C512 (SDA, SCL, WP);endififdef AT24C256 module AT24C256 (SDA, SCL, WP);endififdef AT24C128 module AT24C128 (SDA, SCL, WP);endififdef AT24C64A module AT24C64 (SDA, SCL, WP);endififdef AT24C32A module AT24C32 (SDA, SCL, WP);endififdef AT24C16A module A
13、T24C16A (SDA, SCL, WP);endififdef AT24C08A module AT24C08A (SDA, SCL, WP);endififdef AT24C04A module AT24C04 (SDA, SCL, WP);endififdef AT24C02A module AT24C02A (SDA, SCL, WP);endififdef AT24C01A module AT24C01A (SDA, SCL, WP);endififdef AT24C64 module AT24C64 (SDA, SCL, WP);endififdef AT24C32 module
14、 AT24C32 (SDA, SCL, WP);endififdef AT24C16 module AT24C16 (SDA, SCL, WP);endififdef AT24C08 module AT24C08 (SDA, SCL, WP);endififdef AT24C04 module AT24C04 (SDA, SCL, WP);endififdef AT24C02 module AT24C02 (SDA, SCL, WP);endififdef AT34C02 module AT34C02 (SDA, SCL, WP);endifinout SDA;/ Bi-directional
15、 serial datainput SCL;/ Serial clockinput WP;/ Write protection/ DEVICE CONFIGURATION / Slave address formats/1M1010_0_A1_P0_R/W/512K1010_0_A1_A0_R/W/256K1010_0_A1_A0_R/W/128K1010_0_A1_A0_R/W/64K1010_A2_A1_A0_R/W/32K1010_A2_A2_A0_R/W/16K1010_P1_P1_P0_R/W/8K1010_A2_P1_P0_R/W /4K1010_A2_A1_P0_R/W/2K10
16、10_A2_A1_A0_R/W/1K1010_A2_A1_A0_R/W/ The following parameters configure the device./ The A2_A1_A0 of the slave addresses are arbitrary for the / purpose of testing the model. A testbench must send the indicated/ device address, together with the appropriate memory address bits/ P2_P1_P0, as needed./
17、AT24C1024, 512 pages at 256 bytes/page, 17 address bitsifdef AT24C1024 parameter MEM_SIZE = 131072; parameter ADDR_SIZE = 17; parameter WORD_ADDR_SIZE = 8; parameter SLAVE_ADDRESS = 6b1010_00; / Testbench provides P0 and R/W bitsendif/ AT24C512B, 512 pages at 128 bytes/page, 16 address bits ifdef AT
18、24C512B parameter MEM_SIZE = 65536; parameter ADDR_SIZE = 16; parameter WORD_ADDR_SIZE = 7; parameter SLAVE_ADDRESS = 7b1010_011; / Testbench provides R/W bitendif/ AT24C512, 512 pages at 128 bytes/page, 16 address bits ifdef AT24C512 parameter MEM_SIZE = 65536; parameter ADDR_SIZE = 16; parameter W
19、ORD_ADDR_SIZE = 7; parameter SLAVE_ADDRESS = 7b1010_011; / Testbench provides R/W bitendif/ AT24C256, 512 pages at 64 bytes/page, 15 address bitsifdef AT24C256 parameter MEM_SIZE = 32768; parameter ADDR_SIZE = 15; parameter WORD_ADDR_SIZE = 6; parameter SLAVE_ADDRESS = 7b1010_011; / Testbench provid
20、es R/W bitendif/ AT24C128, 256 pages at 64 bytes/page, 14 address bitsifdef AT24C128 parameter MEM_SIZE = 16384; parameter ADDR_SIZE = 14; parameter WORD_ADDR_SIZE = 6; parameter SLAVE_ADDRESS = 7b1010_011; / Testbench provides R/W bitendif/ AT24C64, 256 pages at 32 bytes/page, 13 address bits ifdef
21、 AT24C64 parameter MEM_SIZE = 8192; parameter ADDR_SIZE = 13; parameter WORD_ADDR_SIZE = 5; parameter SLAVE_ADDRESS = 7b1010_111; / Testbench provides R/W bitendif/ AT24C64A, 256 pages at 32 bytes/page, 13 address bits ifdef AT24C64A parameter MEM_SIZE = 8192; parameter ADDR_SIZE = 13; parameter WOR
22、D_ADDR_SIZE = 5; parameter SLAVE_ADDRESS = 7b1010_111; / Testbench provides R/W bitendif/ AT24C32, 128 pages at 32 bytes/page, 12 address bitsifdef AT24C32 parameter MEM_SIZE = 4096; parameter ADDR_SIZE = 12; parameter WORD_ADDR_SIZE = 5; parameter SLAVE_ADDRESS = 7b1010_101; / Testbench provides R/
23、W bitendif/ AT24C32A, 128 pages at 32 bytes/page, 12 address bitsifdef AT24C32A parameter MEM_SIZE = 4096; parameter ADDR_SIZE = 12; parameter WORD_ADDR_SIZE = 5; parameter SLAVE_ADDRESS = 7b1010_101; / Testbench provides R/W bitendif/ AT24C16, 128 pages at 16 bytes/page, 11 address bitsifdef AT24C1
24、6 parameter MEM_SIZE = 2048; parameter ADDR_SIZE = 11; parameter WORD_ADDR_SIZE = 4; parameter SLAVE_ADDRESS = 4b1010; / Testbench provides P2_P1_P0_R/W bitsendif/ AT24C16A, 128 pages at 16 bytes/page, 11 address bitsifdef AT24C16A parameter MEM_SIZE = 2048; parameter ADDR_SIZE = 11; parameter WORD_
25、ADDR_SIZE = 4; parameter SLAVE_ADDRESS = 4b1010; / Testbench provides P2_P1_P0_R/W bitsendif/ AT24C08, 64 pages at 16 bytes/page, 10 address bits ifdef AT24C08 parameter MEM_SIZE = 1024; parameter ADDR_SIZE = 10; parameter WORD_ADDR_SIZE = 4; parameter SLAVE_ADDRESS = 5b1010_0; / Testbench provides
26、P1_P0_R/W bits endif/ AT24C08A, 64 pages at 16 bytes/page, 10 address bits ifdef AT24C08A parameter MEM_SIZE = 1024; parameter ADDR_SIZE = 10; parameter WORD_ADDR_SIZE = 4; parameter SLAVE_ADDRESS = 5b1010_0; / Testbench provides P1_P0_R/W bits endif/ AT24C04, 32 pages at 16 bytes/page, 9 address bi
27、tsifdef AT24C04 parameter MEM_SIZE = 512; parameter ADDR_SIZE = 9; parameter WORD_ADDR_SIZE = 4; parameter SLAVE_ADDRESS = 6b1010_00; / Testbench provides P0_R/W bits endif/ AT24C04A, 32 pages at 16 bytes/page, 9 address bitsifdef AT24C04A parameter MEM_SIZE = 512; parameter ADDR_SIZE = 9; parameter
28、 WORD_ADDR_SIZE = 4; parameter SLAVE_ADDRESS = 6b1010_00; / Testbench provides P0_R/W bits endif/ AT24C02, 32 pages at 8 bytes/page, 8 address bitsifdef AT24C02 parameter MEM_SIZE = 256; parameter ADDR_SIZE = 8; parameter WORD_ADDR_SIZE = 3; parameter SLAVE_ADDRESS = 7b1010_100; / Testbench provides
29、 R/W bitendif/ AT24C02A, 32 pages at 8 bytes/page, 8 address bitsifdef AT24C02A parameter MEM_SIZE = 256; parameter ADDR_SIZE = 8; parameter WORD_ADDR_SIZE = 3; parameter SLAVE_ADDRESS = 7b1010_100; / Testbench provides R/W bitendif/ AT24C01A, 16 page at 8 bytes/page, 7 address bits ifdef AT24C01A p
30、arameter MEM_SIZE = 128; parameter ADDR_SIZE = 7; parameter WORD_ADDR_SIZE = 3; parameter SLAVE_ADDRESS = 7b1010_110; / Testbench provides R/W bits endif/ AT34C02, 16 pages at 16 bytes/page, 8 address bitsifdef AT34C02 parameter MEM_SIZE = 256; parameter ADDR_SIZE = 8; parameter WORD_ADDR_SIZE = 4;
31、parameter SLAVE_ADDRESS = 7b1010_100; / Testbench provides R/W bitendif/ Device Parameters for internal decoding/ AT24C1024, 512 pages at 256 bytes/page, 17 address bits parameter MEM_SIZE_1MEG_BIT = 131072; parameter ADDR_SIZE_1M_BIT = 17;parameter WORD_ADDR_SIZE_1M_BIT = 8;/ AT24C512B, 512 pages a
32、t 128 bytes/page, 16 address bits parameter MEM_SIZE_500K_BIT = 65536; parameter ADDR_SIZE_500K_BIT = 16;parameter WORD_ADDR_SIZE_500K_BIT = 7;/ Removed to avoid redefinition error at compilation/ AT24C512, 512 pages at 128 bytes/page, 16 address bits / parameter MEM_SIZE_500K_BIT = 65536; / paramet
33、er ADDR_SIZE_500K_BIT = 16;/ parameter WORD_ADDR_SIZE_500K_BIT = 7;/ AT24C256, 512 pages at 64 bytes, 15 address bits parameter MEM_SIZE_256K_BIT = 32768; parameter ADDR_SIZE_256K_BIT = 15;parameter WORD_ADDR_SIZE_256K_BIT = 6;/ AT24C128, 256 pages at 64 bytes, 14 address bits parameter MEM_SIZE_128
34、K_BIT = 16384; parameter ADDR_SIZE_128K_BIT = 14;parameter WORD_ADDR_SIZE_128K_BIT = 6;/ AT24C64, AT24C64A, 256 pages at 32 bytes, 13 address bits parameter MEM_SIZE_64K_BIT = 8192; parameter ADDR_SIZE_64K_BIT = 13;parameter WORD_ADDR_SIZE_64K_BIT = 5;/ AT24C32, AT24C32A, 128 pages at 32 bytes/page,
35、 12 address bits parameter MEM_SIZE_32K_BIT = 4096; parameter ADDR_SIZE_32K_BIT = 12;parameter WORD_ADDR_SIZE_32K_BIT = 5;/ AT24C16, AT24C16A, 128 pages at 16 bytes/page, 11 address bitsparameter MEM_SIZE_16K_BIT = 2048;parameter ADDR_SIZE_16K_BIT = 11;parameter WORD_ADDR_SIZE_16K_BIT = 4;/ AT24C08,
36、 AT24C08A, 64 pages at 16 bytes/page, 10 address bitsparameter MEM_SIZE_8K_BIT = 1024; parameter ADDR_SIZE_8K_BIT = 10;parameter WORD_ADDR_SIZE_8K_BIT = 4;/ AT24C04, AT24C04A, 32 pages at 16 bytes/page, 9 address bits parameter MEM_SIZE_4K_BIT = 512; parameter ADDR_SIZE_4K_BIT = 9;parameter WORD_ADD
37、R_SIZE_4K_BIT = 4;/ AT24C02, AT24C02A 32 pages at 8 bytes/page, 8 address bits parameter MEM_SIZE_2K_BIT = 256; parameter ADDR_SIZE_2K_BIT = 8;parameter WORD_ADDR_SIZE_2K_BIT = 3;/ AT24C01A, 16 pages at 8 bytes/page, 7 ADDRESS bits parameter MEM_SIZE_1K_BIT = 128; parameter ADDR_SIZE_1K_BIT = 7;para
38、meter WORD_ADDR_SIZE_1K_BIT = 3;/ AT34C02, 16 pages at 16 bytes/page, 8 address bits /parameter MEM_SIZE_2K_BIT = 256; /parameter ADDR_SIZE_2K_BIT = 8;parameter WORD_ADDR_SIZE_AT34C02_2K_BIT = 4;parameter BYTE_SIZE = 8; parameter POWER_UP_DELAY = 50000; / For testingparameter VERBOSE = WANT_VERBOSE;
39、/ Enable $display statementsparameter TIMEOUT_FOR_WRITE = 5_000_000;/ 5 ms/parameter TIMEOUT_FOR_WRITE = 0; / For testing/*/*/ Write Protection (Externally applied signal) /*/*/ WP = 0 if not protected/ WP = 1 if protected/*/*/ Registers and Memory /*/*reg (ADDR_SIZE - 1):0 addr_reg ; / address regi
40、sterreg (BYTE_SIZE - 1):0 memory(MEM_SIZE-1):0 ; /Device memoryreg BYTE_SIZE-1: 0 S_Byte_Shft_Reg;reg 6: 0Device_Address;/ Maximum of 7 bitsreg load_address_bit, M_ACK;reg ld_S_Byte_Shft_Reg;reg ld_addr_reg_MSB_byte;reg ld_addr_reg_LSB_byte;reg shift_in;reg shift_out;parameter SEND = 1, RECEIVE = 0;parameter 31:0SENDING = send;parameter 31:0RECEIVING = recv;reg 2:0 state_recv, next_state_recv;reg 2:0 state_send, next_state_send;wireSDA_out;reg S_send_rcvb;reg Addr_Done;reg S_ACK;/ Active-high 3-state/ control of SDA_out reg Valid_Address_flag;
