《Synplicity培训以及试验相关资料.ppt》由会员分享，可在线阅读，更多相关《Synplicity培训以及试验相关资料.ppt（107页珍藏版）》请在三一办公上搜索。
1、,Performance,Advanced Synthesis with theSynplify Pro ToolWinter/Spring 2003Course Outline,IntroductionHDL Coding for Lab 1Technology IndependentAttributesTechnology SpecificAttributes,Advanced SynthesisTopics for Xilinx FPGALab 3MultiPoint Synthesis Flow,Lab 4Advanced SynthesisTopics for Altera CPLD
2、Complex Clocking,Retiming,Lab 2,Lab 5,2,FPGAsolutions,3,s,4,Introduction Introduction,HDL,Coding for Performance,IntroductionSynplicity Solutions,Synplify ASIC,Certify,Introduction,ASIC solutionsSynplicitybrings leading-edgelogic synthesis andverification productsto FPGA and ASICdesigners,Synplify P
3、roand SynplifyAmplifyPhysical Optimizer,5,TM,6,FPGA Product Line OverviewAmplify Physical OptimizerPhysical Synthesis for FPGAs Highest Circuit Performance Fastest Timing Closure Option to Synplify ProSynplify Pro Tool Challenging Designs Complex Projects The Ultimate in FPGASynthesisSynplify Tool F
4、ast Easy to Use Excellent ResultsIntroductionFPGA Synthesis with the Synplify Pro ToolMarket Leader in FPGA Synthesis,Ultra,Fast,uB.E.S.T.,algorithms,Easy,to Use,uLanguage,sensitive,Text EditoruHDL Analyst tooluS.C.O.P.E.,Excellent,Results,uTiming-driven,uDirect,mapping to,technology-specificprimiti
5、vesIntroduction,7,8,Getting HelpOnline Help,u Select,Help-Help,or F1 function key from the Synplify Pro UI,Synplify Pro User Guide,u Pdf,file found in/docs,Synplify Pro Reference Guide,u Pdf,file found in/docs,Synplicity Supportu Synplify Online SupportSOS and Synplify Newsgroup http:/news:/Synplify
6、 First Level Support Can be accessed from S.O.Su Send email to,u Call,the Technical Support Hotline at(408)215-6000,IntroductionHDL Coding for Performance Introduction,HDLHDL Coding Techniques for Performance,Coding for Performance,9,10,Overview,Discuss,various HDL coding issues that affect,performa
7、nce,uShared,Expressions,uShannon,Expansion,uOperand ReorderinguPriority EncodingParallel Case,uRAM,Inferencing,uOther coding issuesLatch GenerationSensitivity ListHDL Coding Techniques for PerformanceCommon Boolean ExpressionsDefinition,u Share,identical boolean(sub-)expressions(&,|,),Pros and Cons,
8、u Saves,Area,u Done,automatically,u Generally have minimal timing impactu Some situations require source code changesmanual replicationWhen to use it,u Share,common expressions to save area(automatic),u Manually replicate expressions to control Large number of loads within a black box Reduce loading
9、 on a critical pathHDL Coding Techniques for Performance,loading,11,12,Common Boolean Expressions Example,uDesign,details,Goal:meet load restriction of 10 Design has two black boxes,each with 8 loads on the en input The Synplify Pro tool does not know about loading within theblack boxes,Original,Des
10、ign,ua_en,and b_en were shared,resulting in 16 loads on en,Fixed,Design,uManually,forced the a_en and b_en to remain separate,uEach enable signal drive only one black box(8 loads)HDL Coding Techniques for PerformanceCommon Boolean Expressionsmodule function_a(in1,in2,en,out),/*synthesis syn_black_bo
11、x*/;input en;input 7:0 in1,in2;output 7:0 out;endmodulemodule function_b(in1,in2,en,out)/*synthesis syn_black_box*/;input en;input 7:0 in1,in2;output 7:0 out;endmodule,module bb_load(a1,a2,b1,b2,opcode,clk,rst,a_out,b_out);input clk,rst;input 3:0 opcode;input 7:0 a1,a2,b1,b2;output 7:0 a_out,b_out;r
12、eg 7:0 a1_reg,a2_reg,b1_reg,b2_reg;wire 3:0 a_opcode;wire 3:0 b_opcode;wire a_en;wire b_en;always(posedge clk or negedge rst),if(!rst)begina1_reg=8h00;a2_reg=8h00;b1_reg=8h00;b2_reg=8h00;endelse begina1_reg=a1;a2_reg=a2;b1_reg=b1;b2_reg=b2;endassign a_opcode=opcode;assign b_opcode=opcode;assign a_en
13、=(a_opcode=4b1011)?1b1:1b0;assign b_en=(b_opcode=4b1011)?1b1:1b0;function_a bb_A(a1_reg,a2_reg,a_en,a_out);function_b bb_B(b1_reg,b2_reg,b_en,b_out);endmodulea_en being shared between function_a and,HDL Coding Techniques for Performance,function_b,causing load on it to be(8+8)=16,13,b,b,14,Common Bo
14、olean Expressions,Applying syn_keep onthe signals a_opcode andb_opcode,divide the loadon the enable signal tomeet the designrequirement.,module function_a(in1,in2,en,out)/*synthesis syn_black_box*/;input en;input 7:0 in1,in2;output 7:0 out;endmodulemodule function_b(in1,in2,en,out)/*synthesis syn_bl
15、ack_box*/;input en;input 7:0 in1,in2;output 7:0 out;endmodule,module bb_load(a1,a2,b1,b2,opcode,clk,rst,a_out,b_out);input clk,rst;input 3:0 opcode;input 7:0 a1,a2,b1,b2;output 7:0 a_out,b_out;reg 7:0 a1_reg,a2_reg,b1_reg,b2_reg;wire 3:0 a_opcode/*synthesis syn_keep=1*/;wire 3:0 b_opcode/*synthesis
16、syn_keep=1*/;wire a_en;wire b_en;always(posedge clk or negedge rst),if(!rst)begina1_reg=8h00;a2_reg=8h00;b1_reg=8h00;b2_reg=8h00;endelse begina1_reg=a1;a2_reg=a2;b1_reg=b1;b2_reg=b2;endassign a_opcode=opcode;assign b_opcode=opcode;assign a_en=(a_opcode=4b1011)?1b1:1b0;assign b_en=(b_opcode=4b1011)?1
17、b1:1b0;function_a bb_A(a1_reg,a2_reg,a_en,a_out);function_b bb_B(b1_reg,b2_reg,b_en,b_out);endmoduleHDL Coding Techniques for PerformanceShannon Expansion Definition,uBoolean,Transformation,F(a,b,c)=aF(0,b,c)+aF(1,b,c),uExample,-F=a+ac(2 to 1 Mux),F(a,b,c)=aF(0,b,c)+aF(1,b,c)a(1b+0c)+a(0b+1c)a+ac,Pr
18、os,and Cons,uCan,dramatically improve timing on critical signals,uMay require substantial changes in the codeuIncreases areaHDL Coding Techniques for Performance,uA,15,16,Shannon Expansion,WhenuPath,to use itis far from meeting timing(25%or more off),If path is within 20%of the goal,try Synthesis an
19、d P&Rconstraints first.,uCritical,path has many logic levels,The Synplify Pro tool may need to break complex paths limitingits ability to prioritize critical signals.small subset of signals have priorityIf all signals feeding a cone of logic are equally critical there isno advantage to prioritize on
20、e over the other.,uNeed,to move critical signals past an operator,The Synplify Pro tool cannot replicate operators(+,-,*,.)HDL Coding Techniques for PerformanceShannon Expansion Example,Design,details,u65,MHz goal,uSignal late has input delay of 8nsutarget technology:Actel 54SX Std,Original,design,u
21、Speed,67.6MHz,Area:35 Cells,Fast,design(prioritize late as much as,possible-Shannon expansion),uSpeed,77.2MHz,Area:42 Cells,HDL Coding Techniques for Performance,17,18,Shannon Expansion Example,Requested Estimated Requested Estimated,module shannon(in0,in1,in2,late,en,out);,Clock,Frequency Frequency
22、 Period,Period Slack,input 7:0 in0,in1,in2;,-System 70.0 MHz 67.6 MHz 14.286 14.785-0.500=,inputoutput,late,en;out;,assign out=(8late|in0)+in1)=in2)endmoduleOriginal source-late traverses an ORgate,an adder,a comparator,and anAND gateHDL Coding Techniques for PerformanceShannon Expansion Example(Con
23、td),Requested Estimated Requested EstimatedClock Frequency Frequency Period Period Slack-System 70.0 MHz 77.2 MHz 14.286 12.949 1.337=,module shannon_fast(in0,in1,in2,late,en,out);input 7:0 in0,in1,in2;input late,en;output out;,wire late_eq_0,late_eq_1;assign late_eq_0=(81b0|in0)+in1)=in2)endmoduleR
24、e-coding using Shannon Expansionreduces the number of levels of logic fromlate to out.HDL Coding Techniques for Performance,A A,uA,19,“,“,20,Operand Reordering Definition,uUse,algebraic identities to prioritize signals,“+B=C”is equivalent to“=C-B”,Pros,and Cons,uCan,dramatically improve timing on cr
25、itical signals,uUsually no area penaltyuRequires minor changes to source code,When,to use it,small subset of signals have priorityuNeed to move critical signals past an operatorHDL Coding Techniques for PerformanceOperand Reordering Example,uDesign,Details,54 MHz goalSignal ADDR has an input delay o
26、f 8nsTarget Technology:Lattice ORCAFPSC,uOriginal,design,39.9 Mhzthe late”signal must traverse an adder and a comparator,Speed:39.9 Mhz,Area:80 cells,uFast,design,Meets timingthe late”signal must traverse only the comparator,Speed:54.3 MhzHDL Coding Techniques for Performance,Area:86 cells,21,22,Lab
27、1,Go,through all the,steps in Lab1HDL Coding Techniques for PerformanceTechnology Independent AttributesTechnology Independent AttributesTechnology Specific AttributesTechnology Independent Attributes,23,“,24,Attributes Overview,Discuss,Technology Independent Attributes,usyn_keep:usyn_preserve:,pres
28、erves netspreserves sequential components,usyn_enum_encoding:determines encoding for enumerateddata types,usyn_state_machine:usyn_encoding:usyn_probe:usyn_direct_enable:,extracts state machine for a stateregisterdetermines encoding for statemachinesmakes an internal net an output portto be used for
29、probingextracts signal as clock enable,to all flip flops it feedsTechnology Independent AttributesGuidelines when Using Attributes in Verilog All attributes are defined in commentstatements and begin with keyword synthesis,Comment,statements directly follow the object,the attribute is being applied
30、on,uBefore,any,”or;”,Leave a space between the object name and thestart of the comment Syntaxobject/*synthesis attribute_name=*/;Technology Independent Attributes,25,26,Guidelines when Using Attributes in VHDL All attributes are defined using the VHDLkeyword attribute The object on which the attribu
31、te is applied isdefined before the value of the attribute is defined,The,type of the attribute is defined,uDefine in the VHDL code before the value of the attribute isdefined,oruUse predefined library package:library synplify;use synplify.attributes.all;Syntax-if package synplify.attributes.all is u
32、sed,this line is not requiredattribute attribute_name:;-define value of attribute-object should be defined before the attribute on it isattribute attribute_name of object:object_type is;Technology Independent Attributessyn_keep Definition,uPreserves Objects,a net throughout synthesis,uApplies,to wir
33、e or reg in Verilog,and signal in VHDL,ValueuBoolean SyntaxuVerilog Usageobject/*synthesis syn_keep=1*/;where object is a wire or reguVHDL Usageattribute syn_keep of object:object_type is true;where object is a single or multi-bit signal.Technology Independent Attributes,u,27,28,syn_keep,Common,Usag
34、e,Prevent certain optimizationsu Prevent sharing of duplicate cells or registersu Preserve a net for simulationu Defining multi-cycle and false paths with-throughoption Note,uApplies,only to nets and should not be applied to,reg or signal that will become sequential devicesTechnology Independent Att
35、ributessyn_keep with Multi-cycle Path,module mult_cyc_path(out,op,opa,opb,clk);input op,clk;input 7:0 opa,opb;output 15:0 out;wire 15:0 muxout;reg sel;reg 15:0 multout/*synthesis syn_keep=1*/;reg 15:0 addout;reg 7:0 add_multa,add_multb;reg 15:0 out;always(posedge clk)beginsel=op;add_multa=opa;add_mu
36、ltb=opb;out=muxout;endalways(add_multa or add_multb)beginmultout=add_multa*add_multb;addout=add_multa+add_multb;endassign muxout15:0=sel?multout:addout;endmoduleTechnology Independent Attributes,Use syn_keep to specify onlymultout as a multi-cycle path.,29,30,syn_keep ExampleUse syn_keep at the inpu
37、t of theregisters to get registered outputs,module example2(out1,out2,clk,in1,in2);,for out1 and out2,output out1,out2;input clk;input in1,in2;wire and_out;wire keep1/*synthesis syn_keep=1*/;wire keep2/*synthesis syn_keep=1*/;reg out1,out2;assign and_out=in1endendmoduleWithout syn_keep out1 and out2
38、optimize into one register.Technology Independent Attributessyn_preserve Definition,uPrevents Objects,sequential optimization,uApplies,to reg or modules in Verilog,signal or,architecture in VHDL ValueuBoolean Syntax,uVerilog,Usage,object/*synthesis syn_preserve=0|1*/;where object can be register def
39、inition signals or modules,uVHDL,Usage,attribute syn_preserve of object:object_type is true|false;where object can be architectures or output ports and internalsignals that hold the value of state registersTechnology Independent Attributes,31,u,u,u,“,“),32,syn_preserve ExampleUse syn_preserve to kee
40、p reg2 andout2 register from getting optimizedmodule syn_preserve(out1,out2,clk,in1,in2)/*synthesis syn_preserve=1*/;output out1,out2;input clk;input in1,in2;reg out1;reg out2;reg reg1;,reg reg2;always(posedge clk)begin,Without syn_preserve reg2 and out2registers are optimized with a warning,reg1=in
41、1 endendmoduleTechnology Independent Attributessyn_enum_encodingDefinitionDefines how enumerated types are implementedObjectsApplies to enumerated types in VHDL,ValueString(“onehot”sequential”gray”or default”Syntax,u,VHDL Usage,type type_name is();attribute syn_enum_encoding of type_name:type is;Tec
42、hnology Independent Attributes,33,34,syn_enum_encoding Example,package testpkg istype mytype is(red,yellow,blue,green,white,violet,indigo,orange);attribute syn_enum_encoding:string;attribute syn_enum_encoding of mytype:type is sequential;end package testpkg;library IEEE;use IEEE.std_logic_1164.all;u
43、se work.testpkg.all;entity decoder isport(sel:in std_logic_vector(2 downto 0);color:out mytype);end decoder;architecture rtl of decoder isWith syn_enum_encoding=“onehot”Technology Independent Attributessyn_state_machineDefinition,beginprocess(sel)begincase sel iswhen 000=color color color color colo
44、r color color color=orange;end case;end process;end rtl;With syn_enum_encoding=“sequential”,u Enables/Disables,state-machine inference,u syn_state_machine overrides the check box for Symbolic FSMCompiler in the Synplify Pro UIObjects,u Applies,to reg in Verilog,signal in VHDL that describes state,re
45、gisters,Valueu BooleanSyntax,u Verilog Usageobject/*synthesis state_machine=0|1*/;where object refers to state registersu VHDL Usageattribute syn_state_machine of object:object_typeis true|false;where object is a state registerTechnology Independent Attributes,35,“,“,“),36,syn_state_machine Example,
46、module FSM1(clk,in1,rst,out1);input clk,rst,in1;output 2:0 out1;reg 2:0 out1;reg 2:0 state/*synthesis syn_state_machine=1*/;reg 2:0 next_state;always(posedge clk or posedge rst)if(rst)state=s0;,syn_state_machine=0,else,state=next_state;,/Combined Next State and Output Logicalways(state or in1)case(s
47、tate)s0:beginout1=3b000;if(in1)next_state=s1;,else,next_state=s0;,ends1:beginout1=3b001;if(in1)next_state=s2;,elseend,next_state=s1;,syn_state_machine=1 causes a state,s2:beginout1=3b010;if(in1)next_state=s3;,machine to be inferred,else,next_state=s2;,enddefault:beginout1=3bxxx;next_state=s0;endendc
48、aseendmoduleTechnology Independent Attributessyn_encodingDefinition,u OverridesObjects,the default FSM compiler encoding,u Applies,to reg in Verilog and signal in VHDL that holds state,values of state machines,Value,u String,(“onehot”gray”sequential”default”or safe”,Syntax,u SCOPE Constraint File Us
49、agedefine_attribute register syn_encoding u Verilog Usageobject/*synthesis syn_encoding=*/;u VHDL Usageattribute syn_encoding of object:object_type is;Technology Independent Attributes,37,38,syn_encoding Example,define read_state 00define write_state 01define delay_state 10module fsm_3states(clock,r
50、eset,ena,read,write);input clock,reset,ena;output read,write;reg read,write;reg 1:0 currentstate/*synthesis syn_encoding=“safe,onehot”*/;reg 1:0 nextstate;/Current State Logicalways(posedge clock or posedge reset)beginif(reset)currentstate=read_state;else currentstate=nextstate;end,/Next State and O
