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1、This material exempt per Department of Commerce license exception TSU,Adding Your Own Peripheral,Objectives,After completing this module,you will be able to:Describe the basic PLB bus transactionsDifferentiate between free-and evaluation-based IP delivered in the EDKIdentify the requirements for int
2、egrating your PeripheralList the steps involved in creating and importing peripherals using Create/Import IP wizardIdentify the limitations of creating peripherals with the wizard,Outline,PLB Bus and InterfacingXPS Directory StructureXPS Peripheral Device FilesIP Delivery in the EDKCreate and Import
3、 Peripheral Wizard,Overview,Peripherals are connected to the microprocessor by using the data and address busesXilinx has implemented the IBM CoreConnect bus architectureProcessor Local Bus(PLB)version 4.6 of the CoreConnect bus architecture is designed for easy connection of on-chip peripheral devi
4、cesAny custom peripheral that connects to the PLB bus must do the following:Meet the principles of the PLB protocol Meet the requirements of the Platform Generator This allows you to take advantage of the simple automated flow that generates system-level architecture,Features,Platform Generator supp
5、orts the following features of the PLB v4.6 for PLB peripherals:32-bit address bus 32,64,or 128-bit data widthSelectable shared bus or point-to-point interconnect topologyPoint-to-point optimization available for one master,1 slave configurationPoint-to-point topology supports 0 cycle latency via ar
6、bitration removalSelectable address pipelining support(2 level only)Watchdog timer for address phase request timeout generationDynamic master request priority based arbitrationVectored resets and address/qualifier registers,Transactions,PLB_Size communicates information about transaction data width,
7、type,and length,as shown below“0000”:single data beat,PLB_BE indicates number of bytes“0001”:4-word cache line“0010”:8-word cache line“0011”:16-word cache line“0100”-”0111”and“1110”“1111”:Reserved“1010”:Word burst transfer“1011”:Double Word burst transfer“1100”:Quad Word burst transfer“1101”:Octal W
8、ord burst transfer,Length of burst specified by PLB_BE,Address and Data Phases,Start of addressphase,Termination of address phase/start of data phase,Example of a Read Transaction(refer to EDK docs for detailed signal descriptions),Termination of read transaction,4-word cachelinetransaction,Address,
9、4 words beingread,Determines ifread(1)or write(0),Point-to-Point Bus Topology,For configurations with single master and single slave(results in reduced address phase),Latency reduced due to eliminationof arbitration and address decodelogic,as well as the interface registersbetween master and slave,C
10、onnecting Devices to the PLB,There are four PLBv46 IPIF modules availableSlave SingleSlave BurstMaster SingleMaster BurstAutomatically generated by create/import peripheral wizard(will cover this later),PLBv46 IPIF templates provided for connecting custom peripherals,Slave Single,Main target use is
11、for register access in the user IP design,Supports 32-bit address and 32-bit data bus Only single Read and Write data transfers are supported No burst transfers,Slave Burst,Main target use is for higher throughput slaves such as memory controllers and bridges,Supports 32-bit address bus and 32-bit,6
12、4-bit,or 128-bit data bus Single Read and Write data transfers,fixed length burst transfers(up to 16 data beats),and cacheline transfers are supported,Master Single,Main target use is for register access in the user IP design,Supports 32-bit address and 32-bit data bus Only single Read and Write dat
13、a transfers are supported No burst transfers Uses reduced LocalLink interface to connect to user IP design,Master Burst,Main target use is for high performance,high data throughput master devices,Supports 32-bit address bus and 32-bit,64-bit,or 128-bit data bus Single Read and Write data transfers a
14、nd fixed length burst transfers(up to 16 data beats)can be initiated to slaves of the same or different sizesWith Master Burst,the User IP reads and writes from the PLB Master via the Xilinx LocalLink Interface Protocol,Outline,PLB Bus and InterfacingXPS Directory StructureXPS Peripheral Device File
15、sIP Delivery in the EDKCreate and Import Peripheral Wizard,Platform Generator searches the following directories for IP:pcores directory(located in theproject directory)MyProcessorIPLib directory(user defined)Repository Directory listed using Project Project Options Device and Repository tab$XILINX_
16、EDK/EDK/hw/XilinxProcessorIPLib/pcores(UNIX)%XILINX_EDK%EDKhwXilinxProcessorIPLibpcores(PC),Peripheral Storage,User peripherals can be located in the project directory or a peripheral repository,Outline,PLB Bus and InterfacingXPS Directory StructureXPS Peripheral Device FilesIP Delivery in the EDK C
17、reate and Import Peripheral Wizard,Simulation Generator,Hardware Platform Generation,Library Generation,Embedded SoftwareDevelopment,ISETools,IP Library or User Repository,MSS,LibGen,.a,Compiler(GCC),.o,Linker(GCC),ELF,MHS,PlatGen,Drivers,MDD,MPD,PAO,PCoreHDL,System andWrapper VHD,system.bmm,Synthes
18、is(XST),NGC,NGDBuild,UCF,NGD,MAP,NCD,PCF,PAR,NCD,BitGen,system.bit,BitInit,download.bit,iMPACT,system_bd.bmm,SimGen,BehavioralVHD Model,SimGen,StructuralVHD Model,SimGen,TimingVHD Model,Simulation,IP Models,ISE Models,TestbenchStimulus,CompEDKLib,CompXLib,ApplicationSource.c,.h,.s,XPS Peripheral Dev
19、ice Files,download.cmd,EDK SWLibraries,XPS Peripheral Device Files,Microprocessor Peripheral Definition(MPD)Provides default parameters and options for peripheral device in XPSPeripheral Analysis Order(PAO)Contains the list of HDL files that are needed for synthesis and defines the analyze order for
20、 compilation Black-Box Definition(BBD)Manages the file locations of optimized hardware netlists for the black-box sections of your peripheral design,MPD File,Peripheral Options,Select various options HDL Language Supported device architectures Supported processors Provide description,MPD File,Bus In
21、terfaces and Parameters,entity xps_gpio is generic(C_BASEADDR:std_logic_vector(0 to 31):=XFFFFFFFF;C_HIGHADDR:std_logic_vector(0 to 31):=X00000000;C_SPLB_AWIDTH:integer range 32 to 36:=32;C_SPLB_DWIDTH:integer range 32 to 128:=32;C_SPLB_P2P:integer range 0 to 1:=0;C_SPLB_MID_WIDTH:integer range 1 to
22、 4:=1;C_SPLB_NUM_MASTERS:integer range 1 to 16:=1;C_SPLB_NATIVE_DWIDTH:integer range 32 to 128:=32;C_SPLB_SUPPORT_BURSTS:integer range 0 to 1:=0;C_FAMILY:string:=virtex5;C_GPIO_WIDTH:integer:=32;C_ALL_INPUTS:integer range 0 to 1:=0;C_INTERRUPT_PRESENT:integer range 0 to 1:=0;C_IS_BIDIR:integer range
23、 0 to 1:=1;C_DOUT_DEFAULT:std_logic_vector:=X0000_0000;C_TRI_DEFAULT:std_logic_vector:=XFFFF_FFFF;C_IS_DUAL:integer range 0 to 1:=0;C_ALL_INPUTS_2:integer range 0 to 1:=0;C_IS_BIDIR_2:integer range 0 to 1:=1;C_DOUT_DEFAULT_2:std_logic_vector:=X0000_0000;C_TRI_DEFAULT_2:std_logic_vector:=XFFFF_FFFF);
24、,Specify possible bus interfaces,Over-rides HDL generics,MPD File,Lists peripheral signal ports that are accessible in XPS,Bus Signals,User data andcontrol signals,PAO File,Update this section,Order of dependency,Contains a list of HDL files required for synthesis,and defines the analyze order for c
25、ompilation,BBD File,The NGC netlists are copied into the project/implementation directoryThe BBD file should have OPTION STYLE=MIX for the tools to copy the filesExample of a single file without options:FILESBlackbox.ngcExample of multiple file selections without options:FILESblackbox1.ngc,blackbox2
26、.ngc,blackbox3.edn,Manages file locations of optimized hardware netlists for black-box sections of the peripheral design,Example of a BBD Filewith multiple file selections,File Usage,Three ways to integrate your own IP into XPS:As a black boxSynthesized with XST or a third-party synthesis toolRequir
27、es MPD and BBD filesBBD file should have OPTION STYLE=MIX As a sourceSynthesized with the rest of the processor systemUses XSTRequires MPD and PAO filesMixUses netlist and source filesRequires MPD,PAO,and BBD filesBBD file should have OPTION STYLE=MIX,Outline,PLB Bus and InterfacingXPS Directory Str
28、uctureXPS Peripheral Device FilesIP Delivery in the EDKCreate and Import Peripheral Wizard,IP Cores,Xilinx has created a wide variety of IP cores:Bus infrastructure coresBusses:PLB,OPBBridges:PLB2OPB,OPB2PLBCommunication:High-Speed10/100 Ethernet MAC,CAN controller,HDLC Interface,Flexray,MOST,USB2Co
29、mmunication:Low-SpeedSerial Peripheral Interface,IIC Interface,UART 16550,UART liteDMA and CounterFixed interval timer,watchdog timer,central DMA controllerMemory Controllers forBlock RAM,DDR/DDR2/SDRAM(multi-port available),SRAM/Flash(multi-port available),Compact FlashGeneral Purpose I/OGeneral Pu
30、rpose I/O(GPIO)Interprocessor CommunicationMailbox,MUTEX,See IP Catalog or Xilinx web for Complete Listing of free and evaluation IP Cores,IP Core Information,The size of each core is available in the data sheetFor example,the opb_ethernetlite_v1_01_b data sheet contains the following table:,Data sh
31、eet provided for each core(right-click on core in IP catalog to access),Processor System Size,The Processor IP Calculator is an online tool that helps you easily estimate the processor IP core size it out!,Outline,PLB Bus and InterfacingXPS Directory StructureXPS Peripheral FilesIP Delivery in the E
32、DKCreate and Import Peripheral Wizard,Create and Import Peripheral Wizard,The wizard helps you create your own peripheral and then import it into your design The wizard generates the necessary core description files into the user-selected directoryYou can start the wizard after creating a new projec
33、t or opening an existing project in XPSThe user peripheral can be imported directly through the wizard by skipping the creation optionEnsure that the peripheral complies with Xilinx implementation of the IBM CoreConnect bus architecture standard,Starting the IP Wizard,The Create and Import Periphera
34、l Wizard can be started after creating a project and using Hardware Create or Import Peripheral or opening an existing project or using Start Programs Xilinx ISE Design Suite 10.1 EDK Accessories Create and Import Peripheral Wizard,Select the Flow and Directory,The project directory assigned as the
35、target directory will allow the peripheral to be available to the project without importing it.User repository will allow multiple projects to access the same peripheral by importing it in a project,Selecting a Peripheral Name and Bus,Provide the peripheral name and version,3,Select the bus to which
36、 the peripheral will attach,4,Selecting Various Functionalities,Configure the Slave Interface,6,Select the functionality,5,Select Software Registers,Configure the SWaccessible registers,7,Select IPIF Signals,Select the IPIF signalsavailable to the user logic,8,Select Optional Bus Functional Model,Op
37、tional Bus Functional ModelSimulation Template,9,Select Optional Implementations Support,Optional Implementation Tools Support,10,You can select to generate HDL in VerilogYou can select to generate project file so you can synthesize using XST and use ISE implementation toolsYou can select to generat
38、e software drivers,Generate Peripheral Template,Finish,11,Since the project directory was assigned as the target directory the peripheral will appear in the IP Catalog under Project Local pcores folder,Importing a Peripheral,Select Import Peripheral flow,Identify the Project Directoryor Repository,1
39、,2,This step is not needed if the peripheral was created in the current project directoryUse this step to import peripherals(make a local copy)created in a shared environment,Custom IP Name and Source,The name of the peripheral must match the top-level entity name or module nameThe user version name
40、 is optional,Source file types can be a combination of HDL sources,netlists,and documentation filesThe top-level HDL must conform to the CoreConnect bus architecture standard,Select HDL Source files,4,Enter the top entity name and version name,3,Custom IP HDL and Location,The HDL language can be VHD
41、L,Verilog,or mixedSource files can already be in a projectSource files can be browsed,Select the libraries and source files in order of dependency,from lowest to highest,Select HDL source files and libraries,6,Select language and browse to source files,5,Bus Interface,If CoreConnect bus architecture
42、 naming conventions are followed,the ports are matched;if not,you must assign them,Verify bus port connections,8,Select bus interface,7,Interrupt Source,Select interrupt source and sensitivity,10,Define bus interface parameters,9,Select interrupting signal source,type(level versus edge),and polarity
43、This will be presented only if interrupt present,Attributes,Select port attributes that require special handling,12,Select parameter attributes that require special handling,11,The parameters are listedView or change the parameter default valuesThe changed value is reflected in the MPD file,The port
44、s area is listedView or change the parameter default valuesThe changed value is reflected in the MPD file,Importing Custom IP,If the netlist and documentation files were selected earlier,the corresponding GUI displays,requesting their locationsIf not,the Finished GUI displaysIf the save box is check
45、ed,the previously generated files will also be saved,The peripheral will appear under the Peripheral or Project Repository folder in the IP Catalog,Knowledge Check,What is the process for creating a peripheral of custom IP in XPS?What is the process for importing a piece of custom IP into XPS?If you
46、 are using a third-party synthesis tool to compile your IP,what files are required to integrate that IP into XPS?,Answers,What is the process for creating a peripheral of custom IP in XPS?Start the Create and Import Wizard tool from XPSSelect the Create templates for a new peripheral optionIdentify
47、the destination directory locationSelect the bus interfaceSelect functionality and any interruptsDefine any software registers and address rangesAdd additional signals which the peripheral may be usingGenerate the filesAdd user logic in user_logic.vhd,Answers,What is the process for incorporating a
48、piece of custom IP into XPS?Develop your custom IP by using any combination of HDL,netlist,or librariesEnsure that the top-level file conforms to CoreConnect bus architecture requirementsStart the Create and Import Wizard tool from XPSIdentify the location of libraries,netlists,and source files in o
49、rder of dependencySelect the bus interfaceSelect the source and any type of interruptIf you are using a third-party synthesis tool to compile your IP,what files are required to integrate that IP into XPS?MPD and BBD files,Where Can I Learn More?,Tool documentationProcessor IP Reference GuideEmbedded System Tools Guide Create/Import Peripheral WizardEmbedded System Tools Guide Microprocessor Peripheral DescriptionEmbedded System Tools Guide Peripheral Analyze OrderXilinx DriversSupport WebsiteEDK Website:,
