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1、Chapter 4Logic design of sequential circuits,Computer Organization,Chapter 4 logic design of sequential circuits,4.1 General model of sequential circuits4.2 Flip-flops4.3 Synthesis of sequential logic circuits4.4 Summary,4.1 General model of sequential circuits,outputs=f（inputs，current states）,Next
2、states=g（inputs，current states）,Synchronous sequential logic circuitsThe current state variables can change values only at discrete fixed time instants.Asynchronous sequential logic circuitsThe current state variables change values in accordance with the change of input variables in a random fashion
3、,not in synchronism with a clock signal.Most of the sequential circuits encountered in computer organization are synchronous circuits.,4.1 General model of sequential circuits,Synchronous sequential logic circuits,Asynchronous sequential logic circuits,4.2 Flip-flops,Analysis of a simple SR latch（SR
4、暂存器）R=0,S=1R=0，S=1 Q=0-Q=1Q=1R=1,S=0 R=1，S=0 Q=1-Q=0Q=0,S QR Q,S,R,Q,-Q=1State 1,-Q=0State 0,4.2 Flip-flops,Analysis of a simple SR latch（SR暂存器）R=0,S=0,Q(t)=0State 0S=0Q(t)=0R=0,S=0,Q(t)=1 State 1Q(t)=1-Q(t+1)=0 R=0,S QR Q,S,R,Q,-Q(t+1)=1-Q(t+1)=0 State no change,-Q(t+1)=1 State no change,Analysis o
5、f a simple SR latch,4.2 Flip-flops,Analysis of a simple SR latch,S QR Q,S,R,Q,4.2 Flip-flops,The reduced state transition table of an SR latch,4.2 Flip-flops,SR Flip-Flop（SR触发器）,The excitation table of an SR flip-flop,S Q clkR Q,4.2 Flip-flops,J-K flip-flop,J，K：inputs；CLK：clock;S：set；CLR：clear；Q：out
6、put,4.2 Flip-flops,D flip-flop,D S Q clk C Q,The reduced state transition table of a D flip-flop,4.3 Synthesis of MSI sequential logic circuits,sequential logic circuits,Write Clock equation,Write Output equation,Write excitation equation,state Equation,Characteristic equation,State transition table
7、,Timing Diagram,State transition diagram,Summarylogic function,4.3 Synthesis of MSI sequential logic circuits,RegisterA register can be constructed with any of the types of flip-flops(J-k flip-flop,D flip-flop and so on),4.3 Synthesis of MSI sequential logic circuits,RegisterA register can be constr
8、ucted with any of the types of flip-flops(J-k flip-flop,D flip-flop and so on),Q3 D CLK,I3,I2,Q2 D CLK,I1,Q1 D CLK,I0,Q0 D CLK,Clock,load,Maintain load,D1 Q1 F1 CLK,Shift register,X1 X2 X3 X4,Shift rightCLK,Serial inputs DIN,waveform of serial input¶llel output right shift register,4.3 Synthesis
9、 of MSI sequential logic circuits,counter,J Q CLK K CLR,J Q CLK K CLR,Q0 Q1 Q2 Q3,clear,1,Clk,J Q CLK K CLR,J Q CLK K CLR,4.3 Synthesis of MSI sequential logic circuits,试分析下图所示的同步时序逻辑电路的逻辑功能。FF0、FF1、FF2是3个JK触发器，时钟脉冲为下降沿触发。,解：写驱动方程和输出方程J0=K0=1 J1=(Q0+Q2)K1=Q0 J2=Q0 Q1 K2=Q0 F=Q0 Q2,求状态方程将各触发器的驱动方程代入到
10、JK触发器的特性方程Q*=JQ+KQ中，得到相应的状态方程J0=K0=1 J1=(Q0+Q2)K1=Q0 J2=Q0 Q1 K2=Q0 F=Q0 Q2 Q0*=Q0 Q1*=Q0 Q2 Q1+Q0Q1 Q2*=Q0 Q1 Q2+Q0 Q2,列状态转换真值表，画状态转换图及时序波形图,Q0*=Q0 Q1*=Q0 Q2 Q1+Q0Q1 Q2*=Q0 Q1 Q2+Q0 Q2,由状态转换表很容易画出状态转换图,Q0,Q1,Q2,F,图6-4 例6-1的波形图,1,0,0,0,1,1,0,有效状态,有效循环,自启动,Summary,4.1 General model of sequential circuits4.2 Flip-flopsSR latchSR Flip-FlopJ-K Flip-FlopD Flip-Flop4.3 Synthesis of sequential logic circuitsRegister(J-K flip-flop or D flip-flop)Shift register(D flip-flop)counter(J-K flip-flop),Combinationalcircuit,memory,inputs,output,Currentstates,Next states,clock,
