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1、湘潭大学计算机组成原理实验一16位运算器module Alu16(T,M,F,C,Z,N,OV); parameter bit_width=16; inputbit_width-1:0T; input1:0M; outputbit_width-1:0F; output Z,C,N,OV; regbit_width:0A,B; regbit_width:0F; reg3:0S; reg16:0F1; reg C,Z,N,OV; initial C=0; always(T,M) case(M) 2b00:A=T15,T; 2b01:B=T15,T; 2b11:S=T3:0; endcase alw
2、ays(A,B,S) begin OV=0; case(S) 4b0001:begin C,F1=A+B;OV=F116F115;end 4b0010:begin C,F1=A-B;OV=F116F115;end 4b0011:begin C,F1=A+1;OV=F116F115;end 4b0100:begin C,F1=A-1;OV=F116F115;end 4b0101:begin C,F1=A&B;end 4b0110:begin C,F1=A|B;end 4b0111:begin C,F1=A;end 4b1000:begin C,F1=A15:0,1b0;end 4b1001:begin C,F1=A15,1B0,A15:1;end 4b1010:begin C,F1=A15:0,1b0;OV=F116F115;end 4b1011:begin C,F1=A16,A16:1;OV=F116F115;end default:F1=0; endcase F=F116:0; Z=(F?1b0:1b1); N=F16; end endmodule
