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1、verilog HDL 语言的数字钟设计module shuzizhong(clk,rst,en,fyx,syx,naozhong,clk2,dsec,sec,kzf,kzs,a,b,c,d,e,f,g,h,kk,aa); input clk,en,fyx,syx,rst,clk2,kzf,kzs,kk,aa; output naozhong; output 3:0 dsec,sec,a,b,c,d,e,f,g,h; reg3:0 cn,dcn,xh,dxh,nf,dnf,ns,dns; reg 3:0 sec,dsec; reg 7:0 qr,qy,qn,data; reg clkn,clk
2、y; reg 3:0 a,b,c,d,e,f,g,h; reg naozhong; reg minclk, hourclk,dayclk,monthclk,yearclk; 显示模块 always (kk) begin if(kk) begin a=dxh; b=xh; c=dcn; d=cn; e=dns; f=ns; g=dnf; h=nf; end else begin a=qn7:4; b=qn3:0; c=0; d=qy7:4; e=qy3:0; f=0; g=qr7:4; h=qr3:0; end end 秒计数和秒校正模块 always(posedge clk or negedg
3、e rst) begin if(!rst) begin sec3:0=4b0000; dsec3:0=4b0000; end else begin if(en=1 & aa=1) begin if(sec3:0=9) begin sec3:0=0; if(dsec3:0=5) begin dsec3:0=0; minclk=1; end else begin dsec3:0=dsec3:0+1b1; minclk=0; end end else begin sec3:0=sec3:0+1b1; minclk=0; end end end end 分计数和分校正模块 always(posedge
4、 clk or negedge rst) begin if(!rst) begin dcn3:0=4b0000; cn3:0=4b0000; end else begin if(minclk=1) begin if(en=1 & aa=1) begin if(cn3:0=9) begin cn3:0=0; if(dcn3:0=5) begin dcn3:0=0; hourclk=1; end else begin dcn3:0=dcn3:0+1b1; hourclk=0; end end else begin cn3:0=cn3:0+1b1; hourclk=0; end end end el
5、se begin if(en=0 & aa=1) begin hourclk=0; if(fyx) begin if(cn9) cn=cn+1b1; else begin cn3:0=4b0000; if(dcn3:05) dcn3:0=dcn3:0+1b1; else dcn3:0=4b0000; end end end end end end 时计数和时校正模块 always(posedge hourclk or negedge rst) begin if(!rst) begin xh3:0=4b0000; dxh3:0=4b0000; end else begin if(hourclk=
6、1) begin if(en=1 & aa=1 ) begin if(xh3:0=3 & dxh3:0=2) begin xh3:0=0; dxh3:0=0; dayclk=1; end else begin dayclk=0; if(xh3:09) xh3:0=xh3:0+1b1; else begin xh3:0=0; if(dxh3:02) dxh3:0=dxh3:0+1b1; else dxh3:0=0; end end end end else begin if (en=0 & aa=1 ) begin if(syx) begin if(xh3:0=3 & dxh3:0=2) beg
7、in xh3:0=0; dxh3:0=0; end else end end end end end 日计数和日校正模块 always(posedge clk or negedge rst) begin if(!rst) begin qr=8b1; end else if(dayclk=1) begin if(en=1 & aa=0) begin monthclk=0; if(qr=data) begin qr=8b1; monthclk=1; end else if(qr3:0=4b1001) begin qr7:4=qr7:4+2b1; qr3:0=4b0; end else qr=qr+
8、2b1; end end begin if(xh3:09) xh3:0=xh3:0+1b1; else begin xh3:0=0; if(dxh3:02) dxh3:0=dxh3:0+1b1; else dxh3:0=0; end end else if(en=0 & aa=0 ) begin if(kzs) begin if(qr7:4=3) begin if (qr3:0=1) begin qr7:4=0; qr3:0=1; end else qr3:0=qr3:0+1b1; end else begin if(qr3:0=9) begin qr3:0=0; qr7:4=qr7:4+1b
9、1; end else qr3:0=qr3:0+1b1; end end end end /月计数器和校正模块 always (posedge clk or negedge rst) begin if(!rst) begin qy=8b1; end else if(monthclk=1) begin if(en=1 & aa=0) begin yearclk=0; if(qy=8b10010) begin qy=8b1; yearclk=1; end else if(qy3:0=4b1001) begin qy7:4=4b1; qy3:0=4b0; end else qy=qy+2b1; en
10、d end else if(en=0 & aa=0) begin if(kzf) begin if(qy7:4=1) begin if(qy3:0=2) begin qy7:4=0; qy3:0=1; end else qy3:0=qy3:0+1b1; end else begin if(qy3:0=9) begin qy3:0=0; qy7:4=qy7:4+1b1; end else qy3:0=qy3:0+1b1; end end end end /data的产生 always begin case(qy) 8b1:data=8b110001; 8b11:data=8b110001; 8b
11、101:data=8b110001; 8b111:data=8b110001; 8b1000:data=8b110001; 8b10000:data=8b110001; 8b10010:data=8b110001; 8b100:data=8b110000; 8b110:data=8b110000; 8b1001:data=8b110000; 8b10001:data=8b110000; 8b10:data=8b101000; endcase end /年计数模块和年校正模块 always (posedge clk or negedge rst) begin if(!rst) begin qn=
12、8b0; end else if(yearclk=1) begin if(en=1 & aa=0) begin if(qn=8b10011001) qn=8b0; else if(qn3:0=4b1001) begin qn7:4=qn7:4+2b1; qn3:0=4b0; end else qn=qn+2b1; end end else if(en=0 & aa=0) begin if(syx) begin if(qn7:4=9) begin if(qn3:0=9) begin qn7:4=0; qn3:0=0; end else qn3:0=qn3:0+1b1; end else begi
13、n if(qn3:0=9) begin qn3:0=0; qn7:4=qn7:4+1b1; end else qn3:0=qn3:0+1b1; end end end end 闹钟模块 always(posedge clk2) begin if(!rst) begin nf3:0=4b0000; dnf3:0=4b0000; ns3:0=4b0000; dns3:0=4b0000; end else if(en) begin if(kzf) begin if(nf9) nf3:0=nf3:0+1b1; else begin nf3:0=4b0000; if(dnf5) dnf=dnf+1b1;
14、 else dnf3:0=4b0000; end end else if(kzs) begin if(dns3:0=2 & ns3:0=3) begin dns=0; ns=0; end else begin if(ns9) ns3:0=ns3:0+1b1; else begin ns3:0=4b0000; if(dns2) dns=dns+1b1; else dns=0; end end end end end always (en) begin if(en) begin if(cn=nf) & (dcn=dnf) & (xh=ns) & (dxh=dns) naozhong=1; else naozhong=0; end end endmodule
