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1、免费单片机温度控制系统中英文翻译资料单片机温度控制系统中英文翻译资料 英文原文 Description The at89s52 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash Programmable and Erasable Read Only Memory (PEROM) and 128 bytes RAM. The device is manufactured using Atmels high density nonvolatile memory technology an
2、d is compatible with the industry standard MCS-51 instruction set and pinout. The chip combines a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel at89s52 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications. Fea
3、tures: Compatible with MCS-51 Products 4K Bytes of In-System Reprogrammable Flash Memory Endurance: 1,000 Write/Erase Cycles Fully Static Operation: 0 Hz to 24 MHz Three-Level Program Memory Lock 128 x 8-Bit Internal RAM 32 Programmable I/O Lines Two 16-Bit Timer/Counters Six Interrupt Sources Progr
4、ammable Serial Channel Low Power Idle and Power Down Modes 单片机温度控制系统中英文翻译资料 The at89s52 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillato
5、r and clock circuitry. In addition, the at89s52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. Th
6、e Power Down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset. Pin Description: VCC Supply voltage. GND Ground. Port 0 单片机温度控制系统中英文翻译资料 Port 0 is an 8-bit open drain bidirectional I/O port. As an output port each pin can sink eig
7、ht TTL inputs. When is are written to port 0 pins, the pins can be used as high impedance inputs. Port 0 may also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode P0 has internal pullups. Port 0 also receives the code byt
8、es during Flash programming, and outputs the code bytes during program verification. External pullups are required during program verification. Port 1 Port 1 is an 8-bit bidirectional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Po
9、rt 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 1 also receives the low-order address bytes during Flash programming and verification. Port 2
10、Port 2 is an 8-bit bidirectional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will sour
11、ce current (IIL) because of the internal pullups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX DPTR). In this application it uses strong internal pull-ups when emitting 1s. During acce
12、sses to external data memory that use 8-bit addresses (MOVX RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification. Port 3 Port 3 is an 8-bit bidirectional I/O port with i
13、nternal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups. Port 3
14、also serves the functions of various special features of the 单片机温度控制系统中英文翻译资料 at89s52 as listed below: Port pin P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 alternate functions rxd (serial input port) txd (serial output port) int0 (external interrupt0) int1 (external interrupt1) t0 (timer0 external input
15、) t1 (timer1 external input) WR (external data memory write strobe) rd (external data memory read strobe) Port 3 also receives some control signals for Flash programming and verification. RST Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. AL
16、E/PROG Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for e
17、xternal timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is
18、weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode. PSEN Program Store Enable is the read strobe to external program memory. When the at89s52 is executing code from external program memory, PSEN is activated twice each machine cycle, ex
19、cept that two PSEN activations are skipped during each access to external data memory. EA/VPP External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is prog
20、rammed, EA will be internally latched on reset. 单片机温度控制系统中英文翻译资料 EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage(VPP) during Flash programming, for parts that require 12-volt VPP. XTAL1 Input to the inverting oscillator ampl
21、ifier and input to the internal clock operating circuit. XTAL2 Output from the inverting oscillator amplifier. Oscillator Characteristics XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1.
22、Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking
23、 circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed. Idle Mode In idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and
24、 all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to
25、two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction foll
26、owing the one that invokes Idle should not be one that writes to a port pin or to external memory. 单片机温度控制系统中英文翻译资料 Status of External Pins During Idle and Power Down Modes mode Program memory ALE psen PortPortPort0 1 2 idle internal 1 data data data 1 Idle External 1 1 float Data data Power down In
27、ternal 0 0 Data Data Data Power down External 0 0 float data Data Power Down Mode In the power down mode the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power down mo
28、de is terminated. The only exit from power down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabili
29、ze. Program Memory Lock Bits On the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below: Lock Bit Protection Modes When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during r
30、eset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is Port3 Data Data Data data 单片机温度控制系统中英文翻译资料 activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the
31、 device to function properly. Programming the Flash： The at89s52 is normally shipped with the on-chip Flash memory array in the erased state (that is, contents = FFH) and ready to be programmed. The programming interface accepts either a high-voltage (12-volt) or a low-voltage (VCC) program enable s
32、ignal. The low voltage programming mode provides a convenient way to program the at89s52 inside the users system, while the high-voltage programming mode is compatible with conventional third party Flash or EPROM programmers. The at89s52 is shipped with either the high-voltage or low-voltage program
33、ming mode enabled. The respective top-side marking and device signature codes are listed in the following table. Vpp=12v Vpp=5v Top-side at89s52 at89s52 mark xxxx xxxx-5 yyww yyww signature (030H)=1EH (030H)=1EH (031H)=51H (031H)=51H (032H)=FFH (032H)=05H The at89s52 code memory array is programmed
34、byte-bybyte in either programming mode. To program any nonblank byte in the on-chip Flash Programmable and Erasable Read Only Memory, the entire memory must be erased using the Chip Erase Mode. Programming Algorithm: Before programming the at89s52, the address, data and control signals should be set
35、 up according to the Flash programming mode table and Figures 3 and 4. To program the at89s52, take the following steps. 1. Input the desired memory location on the address lines. 2. Input the appropriate data byte on the data lines. 3. Activate the correct combination of control signals. 单片机温度控制系统中
36、英文翻译资料 4. Raise EA/VPP to 12V for the high-voltage programming mode. 5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 ms. Repeat steps 1 through 5, changing the address and data for the entire array
37、or until the end of the object file is reached. Data Polling: The at89s52 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written datum on PO.7. Once the write cycle has been completed,
38、true data are valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated. Ready/Busy: The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indi
39、cate BUSY. P3.4 is pulled high again when programming is done to indicate READY. Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of th
40、e lock bits is achieved by observing that their features are enabled. Chip Erase: The entire Flash Programmable and Erasable Read Only Memory array is erased electrically by using the proper combination of control signals and by holding ALE/PROG low for 10 ms. The code array is written with all “1”s
41、. The chip erase operation must be executed before the code memory can be re-programmed. Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except that P3.6 and P3.7 must be pulled to a logic low. The values ret
42、urned are as follows. (030H) = 1EH indicates manufactured by Atmel (031H) = 51H indicates 89C51 (032H) = FFH indicates 12V programming (032H) = 05H indicates 5V programming Programming Interface Every code byte in the Flash array can be written and the entire array can be erased by using the appropr
43、iate combination of control signals. The write operation cycle is selftimed and once initiated, will automatically time itself to completion. 中文翻译 单片机温度控制系统中英文翻译资料 描述 at89s52是美国ATMEL公司生产的低电压，高性能CMOS8位单片机，片内含4Kbytes的快速可擦写的只读程序存储器和128 bytes 的随机存取数据存储器，器件采用ATMEL公司的高密度、非易失性存储技术生产，兼容标准MCS-51产品指令系统，片内置通用8
44、位中央处理器和flish存储单元，功能强大at89s52单片机可为您提供许多高性价比的应用场合，可灵活应用于各种控制领域。 主要性能参数： 与MCS-51产品指令系统完全兼容 4K字节可重复写flash闪速存储器 1000次擦写周期 全静态操作：0HZ24MHZ 三级加密程序存储器 128*8字节内部RAM 32个可编程I/O口 2个16位定时计数器 6个中断源 可编程串行UART通道 低功耗空闲和掉电模式 功能特性概述 AT89S52提供以下标准功能：4K 字节flish闪速存储器，128字节内部RAM，32个I/O口线，两个16位定时计数器，一个5向量两级中断结构，一个全双工串行通信口，片
45、内振荡器及时钟电路。同时，at89s52可降至0HZ的静态逻辑操作，并支持两种软件可选的节电工作模式。空闲方式停止CPU的工作，但允许RAM，定时计数器，串行通信口及中断系统继续工作。掉电方式保存RAM中的内容，但振荡器停止工作并禁止其它所有部件工作直到下一个硬件复位。 单片机温度控制系统中英文翻译资料 方框图 单片机温度控制系统中英文翻译资料 引脚功能说明 Vcc：电源电压 GND：地 P0口：P0口是一组8位漏极开路型双向I/O口，也即地址/数据总线复位口。作为输出口用时，每位能吸收电流的方式驱动8个逻辑门电路，对端口写“1”可 作为高阻抗输入端用。 在访问外部数据存储器或程序存储器时，这
46、组口线分时转换地址和数据总线复用，在访问期间激活内部上拉电阻。 P1口：P1是一个带内部上拉电阻的8位双向I/O口，P1的输出缓冲级可驱动4个TTL逻辑门电路。对端口写“1”，通过内部的上拉电阻把端口拉到高电平，此时可做熟出口。做输出口使用时，因为内部存在上拉电阻，某个引脚被外部信号拉低时会输出一个电流. Flash编程和程序校验期间，P1接受低8位地址。 单片机温度控制系统中英文翻译资料 P2口：P2是一个带有内部上拉电阻的8位双向I/O口，P2的输出缓冲级可驱动4个TTL逻辑门电路。对端口写“1”，通过内部地山拉电阻把端口拉到高电平，此时可作为输出口，作输出口使用时，因为内部存在上拉电阻，
47、某个引脚被外部信号拉低时会输出一个电流。 在访问外部程序存储器获16位地址的外部数据存储器时，P2口送出高8位地址数据。在访问8位地址的外部数据存储器时，P2口线上的内容区中R2寄存器的内容），在整个访问期间不改变。 Flash编程或校验时，P2亦接受高地址和其它控制信号。 P3口：P3口是一组带有内部上拉电阻的8位双向I/O口。P3口输出缓冲级可驱动4个TTL逻辑门电路。对P3口写入“1”时，他们被内部上拉电阻拉高并可作为输出口。做输出端时，被外部拉低的P3口将用上拉电阻输出电流。P3口除了作为一般的I/O口线外，更重要的用途是它的第二功能，如下表所示： 端口引脚 P3.0 P3.1 P3.
48、2 P3.3 P3.4 P3.5 P3.6 P3.7 控制信号。 RST：复位输入。当振荡器工作时，RST引脚出现两个机器周期以上高电平将使单片机复位。 rxd (串行输入口) txd (串行输出口) int0 (外中断0) int1 (外中断1) t0 (定时/计数器0) t1 (定时/计数器1) WR (外部数据存储器写选通) RD (外部数据存储器读选通) 第二功能 P3口还接收一些用于flash闪速存储器编程和程序校验的单片机温度控制系统中英文翻译资料 ALE/PROG：当访问外部程序存储器或数据存储器时，ALE输出脉冲用于所存地址的低8位字节。即使不访问外部存储器，ALE仍以时钟振荡频率的1/6输出固定的正脉冲信号，因此它可对外输出时钟或用于定时目的。要注意的是：每当访问外部数据存储器时将跳过一个ALE脉冲。 对flash存储器编程期间，该引脚还用于输入编程脉冲。 如有不要，可通过对特殊功能寄存器区中的8EH单元的D0位置位，可禁止ALE操作。该外置位后，只要一条MOVX和MOVC指令ALE才会被激活。此外，该引脚会被微弱拉高，单片机执行外部程序时，应设置ALE无效。 PSEN：程序存储允许输出是外部程序存储器的读选通信号，当at89s52由外部程序存储器取指令时，每个机器周期两个PSEN有效，即输出两
