《单片机基础毕业设计外文翻译.docx》由会员分享，可在线阅读，更多相关《单片机基础毕业设计外文翻译.docx（19页珍藏版）》请在三一办公上搜索。
1、单片机基础毕业设计外文翻译本科生毕业设计外文翻译 毕业设计题目： 外文题目：Fundamentals of Single-chip Microcomputer 译文题目：单片机基础 学 院： 信息科学与工程学院 专业班级： 电子信息工程 0802班 学生姓名： 指导教师： 外文原文 Fundamentals of Single-chip Microcomputer Dr. Dobbs MacintoshJournal Abstract The single-chip microcomputer is the culmination of both the development of the
2、digital computer and the integrated circuit arguably the tow most significant inventions of the 20th century . These tow types of architecture are found in single-chip microcomputer. Some employ the split program/data memory of the Harvard architecture, shown in Fig.3-5A-1, others follow the philoso
3、phy, widely adapted for general-purpose computers and microprocessors, of making no logical distinction between program and data memory as in the Princeton architecture. In general terms a single-chip microcomputer is characterized by the incorporation of all the units of a computer into a single de
4、vice. Keyword: Single-chip Microcomputer ROM RAM Programming Algorithm Features Compatible with MCS-51 Products 4K Bytes of In-System Reprogrammable Flash Memory Endurance: 1,000 Write/Erase Cycles Fully Static Operation: 0 Hz to 24 MHz Three-level Program Memory Lock 128 x 8-bit Internal RAM 32 Pro
5、grammable I/O Lines Two 16-bit Timer/Counters Six Interrupt Sources Programmable Serial Channel Low-power Idle and Power-down Modes Description The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4Kbytes of Flash programmable and erasable read only memory (PEROM). The deviceis
6、 manufactured using Atmels high-density nonvolatile memory technology and iscompatible with the industry-standard MCS-51 instruction set and pinout. The on-chipFlash allows the program memory to be reprogrammed in-system or by a conventionalnonvolatile memory programmer. By combining a versatile 8-b
7、it CPU with Flashon a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which providesa highly-flexible and cost-effective solution to many embedded control applications.The AT89C51 provides the following standard features: 4Kbytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bittim
8、er/counters, a five vector two-level interrupt architecture,a full duplex serial port, on-chip oscillator and clock circuitry.In addition, the AT89C51 is designed with static logicfor operation down to zero frequency and supports twosoftware selectable power saving modes. The Idle Modestops the CPU
9、while allowing the RAM, timer/counters,serial port and interrupt system to continue functioning. ThePower-down Mode saves the RAM contents but freezesthe oscillator disabling all other chip functions until the nexthardware reset. Pin Configurations Block Diagram Pin Description VCC Supply voltage. G
10、ND Ground. Port 0 Port 0 is an 8-bit open-drain bi-directional I/O port. As anoutput port, each pin can sink eight TTL inputs. When 1sare written to port 0 pins, the pins can be used as highimpedanceinputs. Port 0 may also be configured to be the multiplexed loworderaddress/data bus during accesses
11、to external programand data memory. In this mode P0 has internalpullups. Port 0 also receives the code bytes during Flash programming,and outputs the code bytes during programverification. External pullups are required during program verification. Port 1 Port 1 is an 8-bit bi-directional I/O port wi
12、th internal pullups.The Port 1 output buffers can sink/source four TTL inputs.When 1s are written to Port 1 pins they are pulled high bythe internal pullups and can be used as inputs. As inputs,Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups
13、.Port 1 also receives the low-order address bytes during Flash programming and verification. Port 2 Port 2 is an 8-bit bi-directional I/O port with internal pullups.The Port 2 output buffers can sink/source four TTL inputs.When 1s are written to Port 2 pins they are pulled high by the internal pullu
14、ps and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit address
15、es (MOVX DPTR). In this application, it uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX RI), Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-order address bits and some control signals d
16、uring Flash programming and verification. Port 3 Port 3 is an 8-bit bi-directional I/O port with internal pullups.The Port 3 output buffers can sink/source four TTL inputs.When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 3 pins
17、 that are externally being pulled low will source current (IIL) because of the pullups.Port 3 also serves the functions of various special features of the AT89C51 as listed below: Port 3 also receives some control signals for Flash programming and verification. ALE/PROG Address Latch Enable output p
18、ulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming.In normal operation ALE is emitted at a constant rate of 1/6the oscillator frequency, and may be used for external timing or clocking purposes. N
19、ote, however, that one ALE pulse is skipped during each access to external Data Memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-dis
20、able bit has no effect if the microcontroller is in external execution mode. PSEN Program Store Enable is the read strobe to external program memory.When the AT89C51 is executing code from external programmemory, PSEN is activated twice each machine cycle, except that two PSEN activations are skippe
21、d during each access to external data memory. EA/VPP External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH.Note, however, that if lock bit 1 is programmed, EA will be internally latched on r
22、eset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming, for parts that require 12-volt VPP. XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit. X
23、TAL2 Output from the inverting oscillator amplifier. Oscillator Characteristics XTAL1 and XTAL2 are the input and output, respectively,of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. T
24、o drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimu
25、m and maximum voltage high and low time specifications must be observed. Idle Mode In idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged durin
26、g this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution,from where it left off, up to two machine cycles before the internal reset algorithm takes
27、 control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that write
28、s to a port pin or to external memory. Figure 1. Oscillator Connections Figure 2. External Clock Drive Configuration Power-down Mode In the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function R
29、egisters retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long e
30、nough to allow the oscillator to restart and stabilize. Program Memory Lock Bits On the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below.When lock bit 1 is programmed, the logic level at the EA pin is sam
31、pled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to functio
32、n properly. Programming the Flash The AT89C51 is normally shipped with the on-chip Flash memory array in the erased state (that is, contents = FFH) and ready to be programmed. The programming interface accepts either a high-voltage (12-volt) or a low-voltage (VCC) program enable signal. The low-volt
33、age programming mode provides a convenient way to program the AT89C51 inside the users system, while the high-voltage programming mode is compatible with conventional thirdparty Flash or EPROM programmers. The AT89C51 is shipped with either the high-voltage or low-voltage programming mode enabled. T
34、he respective top-side marking and device signature codes are listed in the following table. The AT89C51 code memory array is programmed byte-bybyte in either programming mode. To program any nonblank byte in the on-chip Flash Memory, the entire memory must be erased using the Chip Erase Mode. Progr
35、amming Algorithm: Before programming the AT89C51, the address, data and control signals should be set up according to the Flash programming mode table and Figure 3 and Figure 4. To program the AT89C51, take the following steps. 1. Input the desired memory location on the address lines. 2. Input the
36、appropriate data byte on the data lines. 3. Activate the correct combination of control signals. 4. Raise EA/VPP to 12V for the high-voltage programming mode. 5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more
37、than 1.5 ms.Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached. Data Polling: The AT89C51 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result
38、in the complement of the written datum on PO.7. Once the write cycle has been completed, true data are valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated. Ready/Busy: The progress of byte programming can also be monitored by the
39、 RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY. Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and d
40、ata lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled. Chip Erase: The entire Flash array is erased electrically by using the proper combination of control signals and by holding ALE/PROG low for
41、10 ms. The code array is written with all “1”s. The chip erase operation must be executed before the code memory can be re-programmed. Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except that P3.6 and P3.7
42、 must be pulled to a logic low. The values returned are as follows. (030H) = 1EH indicates manufactured by Atmel (031H) = 51H indicates 89C51 (032H) = FFH indicates 12V programming (032H) = 05H indicates 5V programming Programming Interface Every code byte in the Flash array can be written and the e
43、ntire array can be erased by using the appropriate combination of control signals. The write operation cycle is selftimed and once initiated, will automatically time itself to completion. All major programming vendors offer worldwide support for the Atmel microcontroller series. Please contact your
44、local programming vendor for the appropriate software revision. 外文资料翻译译文 单片机基础 摘要：单片机是电脑和集成电路发展的巅峰，有据可查的是它们也是20世纪最 意义的两大发明。 这两种特性在单片机中得到了充分的体现。一些厂家用这两种特性区分程序存储器和数据存储器在硬件中的特性，依据同样的原理广泛的适用于一般目的的电脑和微电脑，一些厂家在程序内存和数据内存之间不区分，像普林斯顿特性。 关键字：单片机 只读存贮器 随机存取存储器 编程方法 AT89C51 主要性能参数： 与MCS-51产品指令系统完全兼容 4K字节可重檫写Fla
45、sh闪速存储器 1000次檫写周期 全静态操作：0HZ-24MHZ 三级加密程序存储器 128*8字节内部RAM 32个可编程I/O口线 2个16位定时/记数器 6个中断源 可编程串行UART通道 低功耗空闲和掉电模式 功能特性概述： AT89C51提供以下标准功能：4K字节Flash闪速存储器，128字节内部RAM，32个I/O口线，两个16位定时/记数器，一个5向量两级中断结构，一个全双工串行通信口，片内振荡器及时钟电路。同时，AT89C51可降至0HZ的静态逻辑操作，并支持两种软件可选的节电工作模式。空闲方式停止CPU的工作，但允许RAM，定时/记数器，串行通信口及中断系统继续工作。掉电
46、方式保存RAM中的内容，但振荡器停止工作直到下一个硬件复位。 AT89C51是美国ATMEL公司生产的低电压，高性能CMOS8位单片机，片内含4k bytes的可反复擦写的只读程序存储器和128 bytes的随机存取数据存储器，器件采用ATMEL公司的高密度、非易失性存储技术生产，兼容标准MCS-51指令系统，片内置通用8位中央处理器和Flash存储单元，功能强大AT89C51单片机可为您提供许多高性价比的应用场合，可灵活应用于各种控制领域。 AT89C51方框图 引脚功能说明 Vcc：电源电压 GND：地 P0 口：P0 口是一组8 位漏极开路型双向IO 口，也即地址数据总线复用口。作为输出
47、口用时，每位能吸收电流的方式驱动8个TTL逻辑门电路，对端口写“1”可作为高阻抗输入端用。在访问外部数据存储器或程序存储器时，这组口线分时转换地址和数据总线复用，在访问期间激活内部上拉电阻。在FIash编程时，P0口接收指令字节，而在程序校验时，输出指令字节，校验时，要求外接上拉电阻。 P1口：P1是一个带内部上拉电阻的8位双向IO口，P1的输出缓冲级可驱动4个TTL逻辑门电路。对端口写“1”，通过内部的上拉电阻把端口拉到高电平，此时可作输入口。作输入口使用时，因为内部存在上拉电阻，某个引脚被外部信号拉低时会输出一个电流。FIash编程和程序校验期间，P1接收低8位地址。 P2口：P2是一个带
48、有内部上拉电阻的8位双向IO口，P2的输出缓冲级可驱动4个TTL逻辑门电路。对端口写“1”，通过内部的上拉电阻把端口拉到高电平，此时可作输入口，作输入口使用时，因为内部存在上拉电阻，某个引脚被外部信号拉低时会输出一个电流。在访问外部程序存储器或16位地址的外部数据存储器时，P2口送出高8位地址数据。在访问8 位地址的外部数据存储器时，P2 口线上的内容区中R2寄存器的内容），在整个访问期间不改变。Flash编程或校验时，P2亦接收高位地址和其它控制信号 P3口：P3口是一组带有内部上拉电阻的8 位双向IO 口。P3 口输出缓冲级可驱动4 个TTL逻辑门电路。对P3 口写入“1”时，它们被内部上拉电阻拉高并可作为输入端口。作输入端时，被外部拉低的P3 口将用上拉电阻输出电流。 P3口除了作为一般的IO口线外，更重要的用途是它的第二功能，如下表所示： P3口还接收一些用于Flash闪速存储器编程和程序校验的控制信号。 RST：复位输入。当振荡器工作时，RST引脚出现两个机器周期以上高电平将使单片机复位。 ALEPROG： 当访问外部程序存储器或数据存储器时，ALE输出脉冲用于锁存地址的低8位字节。即使不访问外部存储器，ALE 仍以时钟振荡频率的l6 输出固定的正脉冲信号，因此它可对外输
