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1、基于TMS320F28335外部中断配置过程void main(void) / Step 1. Initialize System Control: InitSysCtrl; / Step 3. Clear all interrupts and initialize PIE vector table: DINT; /禁止全局中断 InitPieCtrl;/初始化PIE模块 /清除CPU寄存器 IER = 0x0000; IFR = 0x0000; /初始化中断服务表 InitPieVectTable; /指向PIE向量。表注意EALLOW和EDIS的使用，要不中间写的都无效的 EALLOW;
2、/ This is needed to write to EALLOW protected registers PieVectTable.XINT1 = &xint1_isr; PieVectTable.XINT2 = &xint2_isr; EDIS; / This is needed to disable write to EALLOW protected registers / 清除计数 Xint1Count = 0; / Count Xint1 interrupts Xint2Count = 0; / Count XINT2 interrupts LoopCount = 0; / Co
3、unt times through idle loop / Enable Xint1 and XINT2 in the PIE: Group 1 interrupt 4 & 5 / Enable int1 which is connected to WAKEINT: PieCtrlRegs.PIECTRL.bit.ENPIE = 1; / Enable the PIE block PieCtrlRegs.PIEIER1.bit.INTx4 = 1; / Enable PIE Gropu 1 INT4 PieCtrlRegs.PIEIER1.bit.INTx5 = 1; / Enable PIE
4、 Gropu 1 INT5 IER |= M_INT1; / Enable CPU int1 EINT;/使能全局中断 / Enable Global Interrupts /初始化GPIO EALLOW; GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 0; / GPI15 修改 GpioCtrlRegs.GPADIR.bit.GPIO15 = 0; / input GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 0; / Xint1 Synch to SYSCLKOUT only GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 0
5、; / GPIO1 GpioCtrlRegs.GPADIR.bit.GPIO1 = 0; / input GpioCtrlRegs.GPAQSEL1.bit.GPIO1 = 2; / XINT2 Qual using 6 samples GpioCtrlRegs.GPACTRL.bit.QUALPRD0 = 0xFF; / Each sampling window is 510*SYSCLKOUT EDIS; /配置GPIO中断 EALLOW; GpioIntRegs.GPIOXINT1SEL.bit.GPIOSEL = 15; /配置GPIO寄存器GPIOXINT1SEL把GPIO15作为X
6、int1中断 GpioIntRegs.GPIOXINT2SEL.bit.GPIOSEL = 1; / XINT2 is GPIO1 /配置GPIO寄存器GPIOXINT2SEL把GPIO1作为Xint2中断 EDIS; / Configure XINT1 XIntruptRegs.XINT1CR.bit.POLARITY = 0; / Falling edge interrupt XIntruptRegs.XINT2CR.bit.POLARITY = 1; / Rising edge interrupt / Enable XINT1 and XINT2 XIntruptRegs.XINT1CR
7、.bit.ENABLE = 1; / Enable Xint1 XIntruptRegs.XINT2CR.bit.ENABLE = 1; / Enable XINT2 / Step 6. IDLE loop: for(;) interrupt void xint1_isr(void) interrupt void xint2_isr(void) - - GpioDataRegs.GPBCLEAR.all = 0x4; / GPIO34 is low Xint2Count+; PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; GpioDataRegs.GPBCLEA
8、R.all = 0x4; / GPIO34 is low Xint1Count+; PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; void InitPieCtrl(void) / Disable Interrupts at the CPU level: DINT; / Disable the PIE PieCtrlRegs.PIECTRL.bit.ENPIE = 0; /- / EnableInterrupts: / Clear all PIEIFR registers: PieCtrlRegs.PIEIFR1.all = 0; PieCtrlRegs.PIE
9、IFR2.all = 0; PieCtrlRegs.PIEIFR3.all = 0; PieCtrlRegs.PIEIFR4.all = 0; PieCtrlRegs.PIEIFR5.all = 0; PieCtrlRegs.PIEIFR6.all = 0; PieCtrlRegs.PIEIFR7.all = 0; PieCtrlRegs.PIEIFR8.all = 0; PieCtrlRegs.PIEIFR9.all = 0; PieCtrlRegs.PIEIFR10.all = 0; PieCtrlRegs.PIEIFR11.all = 0; PieCtrlRegs.PIEIFR12.al
10、l = 0; / Clear all PIEIER registers: PieCtrlRegs.PIEIER1.all = 0; PieCtrlRegs.PIEIER2.all = 0; PieCtrlRegs.PIEIER3.all = 0; PieCtrlRegs.PIEIER4.all = 0; PieCtrlRegs.PIEIER5.all = 0; PieCtrlRegs.PIEIER6.all = 0; PieCtrlRegs.PIEIER7.all = 0; PieCtrlRegs.PIEIER8.all = 0; PieCtrlRegs.PIEIER9.all = 0; Pi
11、eCtrlRegs.PIEIER10.all = 0; PieCtrlRegs.PIEIER11.all = 0; PieCtrlRegs.PIEIER12.all = 0; /- / This function enables the PIE module and CPU interrupts / void EnableInterrupts / Enable the PIE PieCtrlRegs.PIECTRL.bit.ENPIE = 1; const struct PIE_VECT_TABLE PieVectTableInit = PIE_RESERVED, / 0 Reserved s
12、pace PIE_RESERVED, / 1 Reserved space PIE_RESERVED, / 2 Reserved space PIE_RESERVED, / 3 Reserved space PIE_RESERVED, / 4 Reserved space PIE_RESERVED, / 5 Reserved space PIE_RESERVED, / 6 Reserved space PIE_RESERVED, / 7 Reserved space PIE_RESERVED, / 8 Reserved space PIE_RESERVED, / 9 Reserved spac
13、e PIE_RESERVED, / 10 Reserved space PIE_RESERVED, / 11 Reserved space PIE_RESERVED, / 12 Reserved space / Non-Peripheral Interrupts INT13_ISR, / XINT13 or CPU-Timer 1 INT14_ISR, / CPU-Timer2 DATALOG_ISR, / Datalogging interrupt / Enable Interrupts at the CPU level EINT; / Enables PIE to drive a puls
14、e into the CPU PieCtrlRegs.PIEACK.all = 0xFFFF; RTOSINT_ISR, / RTOS interrupt EMUINT_ISR, / Emulation interrupt NMI_ISR, / Non-maskable interrupt ILLEGAL_ISR, / Illegal operation TRAP USER1_ISR, / User Defined trap 1 USER2_ISR, / User Defined trap 2 USER3_ISR, / User Defined trap 3 USER4_ISR, / User
15、 Defined trap 4 USER5_ISR, / User Defined trap 5 USER6_ISR, / User Defined trap 6 USER7_ISR, / User Defined trap 7 USER8_ISR, / User Defined trap 8 USER9_ISR, / User Defined trap 9 USER10_ISR, / User Defined trap 10 USER11_ISR, / User Defined trap 11 USER12_ISR, / User Defined trap 12 / Group 1 PIE
16、Vectors SEQ1INT_ISR, / 1.1 ADC SEQ2INT_ISR, / 1.2 ADC rsvd_ISR, / 1.3 XINT1_ISR, / 1.4 XINT2_ISR, / 1.5 ADCINT_ISR, / 1.6 ADC TINT0_ISR, / 1.7 Timer 0 WAKEINT_ISR, / 1.8 WD, Low Power / Group 2 PIE Vectors EPWM1_TZINT_ISR, / 2.1 EPWM-1 Trip Zone EPWM2_TZINT_ISR, / 2.2 EPWM-2 Trip Zone EPWM3_TZINT_IS
17、R, / 2.3 EPWM-3 Trip Zone EPWM4_TZINT_ISR, / 2.4 EPWM-4 Trip Zone EPWM5_TZINT_ISR, / 2.5 EPWM-5 Trip Zone EPWM6_TZINT_ISR, / 2.6 EPWM-6 Trip Zone rsvd_ISR, / 2.7 rsvd_ISR, / 2.8 / Group 3 PIE Vectors EPWM1_INT_ISR, / 3.1 EPWM-1 Interrupt EPWM2_INT_ISR, / 3.2 EPWM-2 Interrupt EPWM3_INT_ISR, / 3.3 EPW
18、M-3 Interrupt EPWM4_INT_ISR, / 3.4 EPWM-4 Interrupt EPWM5_INT_ISR, / 3.5 EPWM-5 Interrupt EPWM6_INT_ISR, / 3.6 EPWM-6 Interrupt rsvd_ISR, / 3.7 rsvd_ISR, / 3.8 / Group 4 PIE Vectors ECAP1_INT_ISR, / 4.1 ECAP-1 ECAP2_INT_ISR, / 4.2 ECAP-2 ECAP3_INT_ISR, / 4.3 ECAP-3 ECAP4_INT_ISR, / 4.4 ECAP-4 ECAP5_
19、INT_ISR, / 4.5 ECAP-5 ECAP6_INT_ISR, / 4.6 ECAP-6 rsvd_ISR, / 4.7 rsvd_ISR, / 4.8 / Group 5 PIE Vectors EQEP1_INT_ISR, / 5.1 EQEP-1 EQEP2_INT_ISR, / 5.2 EQEP-2 rsvd_ISR, / 5.3 rsvd_ISR, / 5.4 rsvd_ISR, / 5.5 rsvd_ISR, / 5.6 rsvd_ISR, / 5.7 rsvd_ISR, / 5.8 / Group 6 PIE Vectors SPIRXINTA_ISR, / 6.1 S
20、PI-A SPITXINTA_ISR, / 6.2 SPI-A MRINTA_ISR, / 6.3 McBSP-A MXINTA_ISR, / 6.4 McBSP-A MRINTB_ISR, / 6.5 McBSP-B MXINTB_ISR, / 6.6 McBSP-B rsvd_ISR, / 6.7 rsvd_ISR, / 6.8 / Group 7 PIE Vectors DINTCH1_ISR, / 7.1 DMA channel 1 DINTCH2_ISR, / 7.2 DMA channel 2 DINTCH3_ISR, / 7.3 DMA channel 3 DINTCH4_ISR
21、, / 7.4 DMA channel 4 DINTCH5_ISR, / 7.5 DMA channel 5 DINTCH6_ISR, / 7.6 DMA channel 6 rsvd_ISR, / 7.7 rsvd_ISR, / 7.8 / Group 8 PIE Vectors I2CINT1A_ISR, / 8.1 I2C I2CINT2A_ISR, / 8.2 I2C rsvd_ISR, / 8.3 rsvd_ISR, / 8.4 SCIRXINTC_ISR, / 8.5 SCI-C SCITXINTC_ISR, / 8.6 SCI-C rsvd_ISR, / 8.7 rsvd_ISR
22、, / 8.8 / Group 9 PIE Vectors SCIRXINTA_ISR, / 9.1 SCI-A SCITXINTA_ISR, / 9.2 SCI-A SCIRXINTB_ISR, / 9.3 SCI-B SCITXINTB_ISR, / 9.4 SCI-B ECAN0INTA_ISR, / 9.5 eCAN-A ECAN1INTA_ISR, / 9.6 eCAN-A ECAN0INTB_ISR, / 9.7 eCAN-B ECAN1INTB_ISR, / 9.8 eCAN-B / Group 10 PIE Vectors rsvd_ISR, / 10.1 rsvd_ISR,
23、/ 10.2 rsvd_ISR, / 10.3 rsvd_ISR, / 10.4 rsvd_ISR, / 10.5 rsvd_ISR, / 10.6 rsvd_ISR, / 10.7 rsvd_ISR, / 10.8 / Group 11 PIE Vectors rsvd_ISR, / 11.1 rsvd_ISR, / 11.2 rsvd_ISR, / 11.3 rsvd_ISR, / 11.4 rsvd_ISR, / 11.5 rsvd_ISR, / 11.6 rsvd_ISR, / 11.7 rsvd_ISR, / 11.8 / Group 12 PIE Vectors XINT3_ISR
24、, / 12.1 XINT4_ISR, / 12.2 XINT5_ISR, / 12.3 XINT6_ISR, / 12.4 XINT7_ISR, / 12.5 rsvd_ISR, / 12.6 LVF_ISR, / 12.7 LUF_ISR, / 12.8 ; /- / InitPieVectTable: /- / This function initializes the PIE vector table to a known state. / This function must be executed after boot time. / void InitPieVectTable(void) / Enable the PIE Vector Table PieCtrlRegs.PIECTRL.bit.ENPIE = 1; int16 i; Uint32 *Source = (void *) &PieVectTableInit; Uint32 *Dest = (void *) &PieVectTable; EALLOW; for(i=0; i 128; i+) *Dest+ = *Source+; EDIS;
