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1、局域网交换机毕业论文中英文资料外文翻译文献中英文资料 局域网交换机毕业论文 中英文资料外文翻译文献 英文资料翻译 LAN Switch Architecture This chapter introduces many of the concepts behind LAN switching common to all switch vendors. The chapter begins by looking at how data are received by a switch, followed by mechanisms used to switch data as efficient
2、ly as possible, and concludes with forwarding data toward their destinations. These concepts are not specific to Cisco and are valid when examining the capabilities of any LAN switch. 1. Receiving DataSwitching Modes The first step in LAN switching is receiving the frame or packet, depending on the
3、capabilities of the switch, from the transmitting device or host. Switches making forwarding decisions only at Layer 2 of the OSI model refer to data as frames, while switches making forwarding decisions at Layer 3 and above refer to data as packets. This chapters examination of switching begins fro
4、m a Layer 2 point of view. Depending on the model, varying amounts of each frame are stored and examined before being switched. Three types of switching modes have been supported on Catalyst switches: Cut through Fragment free Store and forward These three switching modes differ in how much of the f
5、rame is received and examined by the switch before a forwarding decision is made. The next sections describe each mode in detail. 1.1 Cut-Through Mode Switches operating in cut-through mode receive and examine only the first 6 bytes of a frame. These first 6 bytes represent the destination MAC addre
6、ss of the frame, which is sufficient information to make a forwarding decision. Although cut-through switching offers the least latency when transmitting frames, it is susceptible to transmitting fragments created via Ethernet collisions, runts (frames less than 64 bytes), or damaged frames. 1.2 Fra
7、gment-Free Mode Switches operating in fragment-free mode receive and examine the first 64 bytes of frame. Fragment free is referred to as fast forward mode in some Cisco Catalyst documentation. Why examine 64 bytes? In a properly designed Ethernet network, collision fragments must be detected in the
8、 first 64 bytes. 1.3 Store-and-Forward Mode 1 中英文资料 Switches operating in store-and-forward mode receive and examine the entire frame, resulting in the most error-free type of switching. As switches utilizing faster processor and application-specific integrated circuits (ASICs) were introduced, the
9、need to support cut-through and fragment-free switching was no longer necessary. As a result, all new Cisco Catalyst switches utilize store-and-forward switching. Figure2-1 compares each of the switching modes. Figure2-1.Switching Modes 2. Switching Data Regardless of how many bytes of each frame ar
10、e examined by the switch, the frame must eventually be switched from the input or ingress port to one or more output or egress ports. A switch fabric is a general term for the communication channels used by the switch to transport frames, carry forwarding decision information, and relay management i
11、nformation throughout the switch. A comparison could be made between the switching fabric in a Catalyst switch and a transmission on an automobile. In an automobile, the transmission is responsible for relaying power from the engine to the wheels of the car. In a Catalyst switch, the switch fabric i
12、s responsible for relaying frames from an input or ingress port to one or more output or egress ports. Regardless of model, whenever a new switching platform is introduced, the documentation will generally refer to the transmission as the switching fabric. Although a variety of techniques have been
13、used to implement switching fabrics on Cisco Catalyst platforms, two major architectures of switch fabrics are common: Shared bus Crossbar 2.1 Shared Bus Switching In a shared bus architecture, all line modules in the switch share one data path. A central arbiter determines how and when to grant req
14、uests for access to the bus from each line card. Various methods of achieving fairness can be used by the arbiter depending on the configuration of the switch. A shared bus architecture is much like multiple lines at an airport ticket counter, with only one ticketing agent processing customers at an
15、y given time. Figure2-2illustrates a round-robin servicing of frames as they enter a switch. Round-robin is the simplest method of servicing frames in the order in which they are received. Current Catalyst switching platforms such as the Catalyst 6500 support a variety of quality of service (QoS) fe
16、atures to provide priority service to specified traffic flows. Figure 2-2. Round-Robin Service Order The following list and Figure 2-3 illustrate the basic concept of moving frames from the received port or ingress, to the transmit port(s) or egress using a shared bus architecture: Frame received fr
17、om Host1 The ingress port on the switch receives the entire frame from Host1 and stores it in a receive buffer. The port checks the frames Frame Check Sequence (FCS) for errors. If the frame is defective (runt, fragment, invalid CRC, or Giant), the port discards the frame and increments the appropri
18、ate counter. Requesting access to the data bus A header containing information necessary to make a forwarding decision is added to the frame. The line card then requests access or permission to transmit the frame onto 2 中英文资料 the data bus. Frame transmitted onto the data bus After the central arbite
19、r grants access, the frame is transmitted onto the data bus. Frame is received by all ports In a shared bus architecture, every frame transmitted is received by all ports simultaneously. In addition, the frame is received by the hardware necessary to make a forwarding decision. Switch determines whi
20、ch port(s) should transmit the frame The information added to the frame in step 2 is used to determine which ports should transmit the frame. In some cases, frames with either an unknown destination MAC address or a broadcast frame, the switch will transmit the frame out all ports except the one on
21、which the frame was received. Port(s) instructed to transmit, remaining ports discard the frame Based on the decision in step 5, a certain port or ports is told to transmit the frame while the rest are told to discard or flush the frame. Egress port transmits the frame to Host2 In this example, it i
22、s assumed that the location of Host2 is known to the switch and only the port connecting to Host2 transmits the frame. One advantage of a shared bus architecture is every port except the ingress port receives a copy of the frame automatically, easily enabling multicast and broadcast traffic without
23、the need to replicate the frames for each port. This example is greatly simplified and will be discussed in detail for Catalyst platforms that utilize a shared bus architecture in Chapter 3, Catalyst Switching Architecture. Figure 2-3. Frame Flow in a Shared Bus 2.2 Crossbar Switching In the shared
24、bus architecture example, the speed of the shared data bus determines much of the overall traffic handling capacity of the switch. Because the bus is shared, line cards must wait their turns to communicate, and this limits overall bandwidth. A solution to the limitations imposed by the shared bus ar
25、chitecture is the implementation of a crossbar switch fabric, as shown in Figure 2-4. The term crossbar means different things on different switch platforms, but essentially indicates multiple data channels or paths between line cards that can be used simultaneously. In the case of the Cisco Catalys
26、t 5500 series, one of the first crossbar architectures advertised by Cisco, three individual 1.2-Gbps data buses are implemented. Newer Catalyst 5500 series line cards have the necessary connector pins to connect to all three buses simultaneously, taking advantage of 3.6 Gbps of aggregate bandwidth.
27、 Legacy line cards from the Catalyst 5000 are still compatible with the Catalyst 5500 series by connecting to only one of the three data buses. Access to all three buses is required by Gigabit Ethernet cards on the Catalyst 5500 platform. A crossbar fabric on the Catalyst 6500 series is enabled with
28、 the Switch Fabric Module (SFM) and Switch Fabric Module 2 (SFM2). The SFM provides 128 Gbps of bandwidth (256 Gbps full duplex) to line cards via 16 individual 8-Gbps connections to the crossbar switch fabric. The SFM2 was introduced to support the Catalyst 6513 13-slot chassis and includes archite
29、cture optimizations over the SFM. Figure 2-4. Crossbar Switch Fabric 3. Buffering Data 3 中英文资料 Frames must wait their turn for the central arbiter before being transmitted in shared bus architectures. Frames can also potentially be delayed when congestion occurs in a crossbar switch fabric. As a res
30、ult, frames must be buffered until transmitted. Without an effective buffering scheme, frames are more likely to be dropped anytime traffic oversubscription or congestion occurs. Buffers get used when more traffic is forwarded to a port than it can transmit. Reasons for this include the following: S
31、peed mismatch between ingress and egress ports Multiple input ports feeding a single output port Half-duplex collisions on an output port A combination of all the above To prevent frames from being dropped, two common types of memory management are used with Catalyst switches: Port buffered memory S
32、hared memory 3.1 Port Buffered Memory Switches utilizing port buffered memory, such as the Catalyst 5000, provide each Ethernet port with a certain amount of high-speed memory to buffer frames until transmitted. A disadvantage of port buffered memory is the dropping of frames when a port runs out of
33、 buffers. One method of maximizing the benefits of buffers is the use of flexible buffer sizes. Catalyst 5000 Ethernet line card port buffer memory is flexible and can create frame buffers for any frame size, making the most of the available buffer memory. Catalyst 5000 Ethernet cards that use the S
34、AINT ASIC contain 192 KB of buffer memory per port, 24 kbps for receive or input buffers, and 168 KB for transmit or output buffers. Using the 168 KB of transmit buffers, each port can create as many as 2500 64-byte buffers. With most of the buffers in use as an output queue, the Catalyst 5000 famil
35、y has eliminated head-of-line blocking issues. (You learn more about head-of-line blocking later in this chapter in the section Congestion and Head-of-Line Blocking.) In normal operations, the input queue is never used for more than one frame, because the switching bus runs at a high speed. Figure 2
36、-5illustrates port buffered memory. Figure 2-5. Port Buffered Memory 3.2 Shared Memory Some of the earliest Cisco switches use a shared memory design for port buffering. Switches using a shared memory architecture provide all ports access to that memory at the same time in the form of shared frame o
37、r packet buffers. All ingress frames are stored in a shared memory pool until the egress ports are ready to transmit. Switches dynamically allocate the shared memory in the form of buffers, accommodating ports with high amounts of ingress traffic, without allocating unnecessary buffers for idle port
38、s. The Catalyst 1200 series switch is an early example of a shared memory switch. The Catalyst 1200 supports both Ethernet and FDDI and has 4 MB of shared packet dynamic random-access memory (DRAM). Packets are handled first in, first out (FIFO). More recent examples of switches using shared memory
39、architectures are the Catalyst 4000 and 4500 series switches. The Catalyst 4000 with a Supervisor I utilizes 8 MB of Static RAM (SRAM) as dynamic frame buffers. All frames are switched using a central processor or ASIC and are stored in packet buffers until 4 中英文资料 switched. The Catalyst 4000 Superv
40、isor I can create approximately 4000 shared packet buffers. The Catalyst 4500 Supervisor IV, for example, utilizes 16 MB of SRAM for packet buffers. Shared memory buffer sizes may vary depending on the platform, but are most often allocated in increments ranging from 64 to 256 bytes. Figure 2-6 illu
41、strates how incoming frames are stored in 64-byte increments in shared memory until switched by the switching engine. Figure 2-6. Shared Memory Architecture 4. Oversubscribing the Switch Fabric Switch manufacturers use the term non-blocking to indicate that some or all the switched ports have connec
42、tions to the switch fabric equal to their line speed. For example, an 8-port Gigabit Ethernet module would require 8 Gb of bandwidth into the switch fabric for the ports to be considered non-blocking. All but the highest end switching platforms and configurations have the potential of oversubscribin
43、g access to the switching fabric. Depending on the application, oversubscribing ports may or may not be an issue. For example, a 10/100/1000 48-port Gigabit Ethernet module with all ports running at 1 Gbps would require 48 Gbps of bandwidth into the switch fabric. If many or all ports were connected
44、 to high-speed file servers capable of generating consistent streams of traffic, this one-line module could outstrip the bandwidth of the entire switching fabric. If the module is connected entirely to end-user workstations with lower bandwidth requirements, a card that oversubscribes the switch fab
45、ric may not significantly impact performance. Cisco offers both non-blocking and blocking configurations on various platforms, depending on bandwidth requirements. Check the specifications of each platform and the available line cards to determine the aggregate bandwidth of the connection into the s
46、witch fabric. 5. Congestion and Head-of-Line Blocking Head-of-line blocking occurs whenever traffic waiting to be transmitted prevents or blocks traffic destined elsewhere from being transmitted. Head-of-line blocking occurs most often when multiple high-speed data sources are sending to the same de
47、stination. In the earlier shared bus example, the central arbiter used the round-robin service approach to moving traffic from one line card to another. Ports on each line card request access to transmit via a local arbiter. In turn, each line cards local arbiter waits its turn for the central arbit
48、er to grant access to the switching bus. Once access is granted to the transmitting line card, the central arbiter has to wait for the receiving line card to fully receive the frames before servicing the next request in line. The situation is not much different than needing to make a simple deposit
49、at a bank having one teller and many lines, while the person being helped is conducting a complex transaction. In Figure 2-7, a congestion scenario is created using a traffic generator. Port 1 on the traffic generator is connected to Port 1 on the switch, generating traffic at a 50 percent rate, destined for both Ports 3 and 4. Port 2 on the traffic generator is connected to Port 2 on the s
