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1、1,Advanced Packaging Tech,2,Outline,Package Development Trend3D Package WLCSP&Flip Chip Package,3,Package Development Trend,4,SO Family,QFP Family,BGA Family,Package Development Trend,5,CSP Family,Memory Card,SiP Module,Package Development Trend,6,3D Package,3D Package,7,3D Package Introduction,Func
2、tional Integration,High,Low,2 Chip StackWirebond,2 Chip StackFlip Chip&Wirebond,Multi ChipStack,Package onPackage(PoP)Stacking,PS-fcCSP+SCSP,Paper Thin,PiP,PoP QFN,8,Stacked Die,Top die,Bottom die,FOW materil,Wire,9,TSV,TSV(Through Silicon Via)A through-silicon via(TSV)is a vertical electrical conne
3、ction(via)passing completely through a silicon wafer or die.TSV technology is important in creating 3D packages and 3D integrated circuits.A 3D package(System in Package,Chip Stack MCM,etc.)contains two or more chips(integrated circuits)stacked vertically so that they occupy less space.In most 3D pa
4、ckages,the stacked chips are wired together along their edges.This edge wiring slightly increases the length and width of the package and usually requires an extra“interposer”layer between the chips.In some new 3D packages,through-silicon via replace edge wiring by creating vertical connections thro
5、ugh the body of the chips.The resulting package has no added length or thickness.,Wire Bonding Stacked Die,10,Whats PoP?PoP is Package on PackageTop and bottom packages are tested separately by device manufacturer or subcon.,PoP,11,PoP,PS-vfBGA,PS-etCSP,Low Loop Wire,Pin Gate Mold,Package Stacking,W
6、afer Thinning,PoP Core Technology,12,PoP,Allows for warpage reduction by utilizing fully-molded structureMore compatible with substrate thickness reductionProvides fine pitch top package interface with thru mold viaImproved board level reliabilityLarger die size/package size ratioCompatible with fli
7、p chip,wire bond,or stacked die configurationsCost effective compared to alternative next generation solutions,Amkors TMV PoP,13,PoP,Ball Placement on top surface,Ball Placement on bottom,Die Bond,Mold(Under Full optional),Laser drilling,Singulation Final Visual Inspection,Base Mtl,Thermal effect,Pr
8、ocess Flow of TMV PoP,14,Digital(Btm die)+Analog(Middle die)+Memory(Top pkg)Potable Digital GadgetCellular Phone,Digital Still Camera,Potable Game Unit,Memory die,Analog die,Digital die,spacer,Epoxy,PiP,15,Easy system integrationFlexible memory configuration100%memory KGDThinner package than POPHigh
9、 IO interconnection than POPSmall footprint in CSP format,It has standardball size and pitch,Constructed with:Film Adhesive die attach Epoxy paste for Top PKG Au wire bonding for interconnection Mold encapsulation,Why PiP?,PiP,16,Material for High Reliability Based on Low Warpage,Wafer Thinning,Fine
10、 Process ControlTop Package AttachDie Attachetc,Optimized Package Design,Flip Chip,Under-fill,Top epoxy,ISM,PiP Core Technology,PiP,17,Analog,WB PIP,FC PIP,PiP,PiP W/B PiP and FC PiP,18,WLCSP&Flip Chip Package,19,WLCSP,What is WLCSP?WLCSP(Wafer Level Chip Scale Packaging),is not same as traditional
11、packaging method(dicing packaging testing,package size is at least 20%increased compared to die size).WLCSP is packaging and testing on wafer base,and dicing later.So the package size is exactly same as bare die size.WLCSP can make ultra small package size,and high electrical performance because of
12、the short interconnection.,20,WLCSP,Why WLCSP?Smallest package size:WLCSP have the smallest package size against die size.So it has widely use in mobile devices.High electrical performance:because of the short and thick trace routing in RDL,it gives high SI and reduced IR drop.High thermal performan
13、ce:since there is no plastic or ceramic molding cap,heat from die can easily spread out.Low cost:no need substrate,only one time testing.WLCSPs disadvantageBecause of the die size and pin pitch limitation,IO quantity is limited(usually less than 50pins).Because of the RDL,stagger IO is not allowed f
14、or WLCSP.,21,RDL,RDL:Redistribution LayerA redistribution layer(RDL)is a set of traces built up on a wafers active surface to re-route the bond pads.This is done to increase the spacing between each interconnection(bump).,22,WLCSP,Process Flow of WLCSP,23,WLCSP,Process Flow of WLCSP,24,Flip Chip Pac
15、kage,FCBGA(Passive Integrated Flip Chip BGA),(PI)-EHS-FCBGA(Passive Integrated Exposed Heat Sink Flip Chip BGA),(PI)-EHS2-FCBGA(Passive Integrated Exposed 2 pieces of Heat Sink Flip Chip BGA),MCM-FCBGA(Multi-Chip-Module FCBGA),PI-EHS-MP-FCBGA(Passive Integrated Exposed Heat Sink Multi Package Flip C
16、hip),25,Bump,26,Bump Development,27,Bump Development,28,Bump Development,29,C4 Flip Chip,Whats C4 Flip Chip?C4 is:Controlled Collapsed Chip ConnectionChip is connected to substrate by RDL and BumpBump material type:solder,gold,30,C4 Flip Chip BGA,Main Features Ball Pitch:0.4mm-1.27mmPackage size:up
17、to 55mmx55mmSubstrate layer:4-16 LayersBall Count:up to 2912 Target Market:CPU、FPGA、Processor、Chipset、Memory、Router、Switches、and DSP etc.,Main Benefits Reduced Signal InductanceReduced Power/Ground InductanceHigher Signal DensityDie Shrink&Reduced Package FootprintHigh Speed and High thermal support
18、,31,C2 Flip Chip,Whats C2 Flip Chip?C2 is:Chip ConnectionChip is connected to substrate by copper postBump material type:copper post with solder plating,Silicon Die,Copper post,Solder,32,C2 Flip Chip,Process Flow of C2,33,C2 Flip Chip,Comparison:C2 Vs C4In some cases,C2 can replace C4 or wire bonding package.,34,Thanks!,
