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1、AT89C51外文翻译DescriptionThe AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash Programmable and Erasable Read Only Memory (PEROM). The device is manufactured using Atmels high density nonvolatile memory technology and is compatible with the industry standard MCS-5
2、1 instruction-set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly flexibl
3、e and cost effective solution to many embedded control applications.Features Compatible with MCS-51 Products 4K Bytes of In-System Reprogrammable Flash Memory Endurance: 1,000 Write/Erase Cycles Fully Static Operation: 0 Hz to 24 MHz Three-Level Program Memory Lock 128 x 8-Bit Internal RAM 32 Progra
4、mmable I/O Lines Two 16-Bit Timer/Counters Six Interrupt Sources Programmable Serial Channel Low Power Idle and Power Down ModesThe AT89C51 provides the following standard features: 4K bytes of Flash,128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt archite
5、cture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial po
6、rt and interrupt system to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.VCCSupply voltage.GNDGround.Port 0Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin
7、 can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 may also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode P0 has internal pullups.Port 0 also receives
8、 the code bytes during Flash programming, and outputs the code bytes during program verification. External pullups are required during program verification. Port 1Port 1 is an 8-bit bi-directional I/O port with internal pullups.The Port 1 output buffers can sink/source four TTL inputs.When 1s are wr
9、itten to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 1 also receives the low-order address bytes during Flash programming and verification
10、. Port 2Port 2 is an 8-bit bi-directional I/O port with internal pullups.The Port 2 output buffers can sink/source four TTL inputs.When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 2 pins that are externally being pulled low wil
11、l source current (IIL) because of the internal pullups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX DPTR). In this application, it uses strong internal pullups when emitting 1s. Durin
12、g accesses to external data memory that use 8-bit addresses (MOVX RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3Port 3 is an 8-bit bi-directional I/O port w
13、ith internal pullups. The Port 3 output buffers can sink/source four TTL inputs.When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups. Port
14、 3 also serves the functions of various special features of the AT89C51 as listed below:Port 3 also receives some control signals for Flash programming and verification. RSTReset input. A high on this pin for two machine cycles while the oscillator is running resets the device. ALE/PROGAddress Latch
15、 Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or cl
16、ocking purposes. Note, however, that one ALE pulse is skipped during each access to external DataMemory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. S
17、etting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSENProgram Store Enable is the read strobe to external program memory. When the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN acti
18、vations are skipped during each access to external data memory. EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH.Note, however, that if lock bit 1 is programmed, EA will be intern
19、ally latched on reset. EA should be strapped to VCC for internal program executions.This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming, for parts that require 12-volt VPP.XTAL1Input to the inverting oscillator amplifier and input to the internal clock operat
20、ing circuit. XTAL2Output from the inverting oscillator amplifier.Oscillator Characteristics XTAL1 and XTAL2 are the input and output, respectively,of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator ma
21、y be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2.There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop,
22、 but minimum and maximum voltage high and low time specifications must be observed.Idle Mode In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unch
23、anged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset alg
24、orithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be on
25、e that writes to a port pin or to external memory.Figure 1. Oscillator ConnectionsNote: C1, C2 = 30 pF 10 pF for Crystals= 40 pF 10 pF for Ceramic ResonatorsFigure 2. External Clock Drive ConfigurationPower-down Mode In the power-down mode, the oscillator is stopped, and the instruction that invokes
26、 power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated
27、 before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.Program Memory Lock Bits On the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in
28、the table below.When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in ag
29、reement with the current logic level at that pin in order for the device to function properly.Programming the Flash The AT89C51 is normally shipped with the on-chip Flash memory array in the erased state (that is, contents = FFH)and ready to be programmed. The programming interface accepts either a
30、high-voltage (12-volt) or a low-voltage (VCC) program enable signal. The low-voltage programming mode provides a convenient way to program the AT89C51 inside the users system, while the high-voltage programming mode is compatible with conventional thirdparty Flash or EPROM programmers.The AT89C51 is
31、 shipped with either the high-voltage or low-voltage programming mode enabled. The respective top-side marking and device signature codes are listed in the following table.The AT89C51 code memory array is programmed byte-by-byte in either programming mode. To program any non-blank byte in the on-chi
32、p Flash Memory, the entire memory must be erased using the Chip Erase Mode. Programming Algorithm: Before programming the AT89C51, the address, data and control signals should be set up according to the Flash programming mode table and Figures 3 and 4. To program the AT89C51, take the following step
33、s.1. Input the desired memory location on the address lines.2. Input the appropriate data byte on the data lines. 3. Activate the correct combination of control signals.4. Raise EA/VPP to 12V for the high-voltage programming mode. 5. Pulse ALE/PROG once to program a byte in the Flash array or the lo
34、ck bits. The byte-write cycle is self-timedand typically takes no more than 1.5 ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached.Data Polling: The AT89C51 features Data Polling to indicate the end of a write cycle. During
35、 a write cycle, anattempted read of the last byte written will result in the complement of the written datum on PO.7. Once the write cycle has been completed, true data are valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated. Rea
36、dy/Busy: The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY.Program Verify: If lock bits LB1 and LB2 have not been progra
37、mmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled. Chip Erase: The entire Flash array is erased electrically by using the p
38、roper combination of control signals and by holding ALE/PROG low for 10 ms. The code array is written with all “1”s. The chip erase operation must be executed before the code memory can be re-programmed.Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verif
39、ication of locations 030H, 031H, and 032H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned are as follows. (030H) = 1EH indicates manufactured by Atmel (031H) = 51H indicates 89C51 (032H) = FFH indicates 12V programming (032H) = 05H indicates 5V programmingProgramming In
40、terfaceEvery code byte in the Flash array can be written and the entire array can be erased by using the appropriate combination of control signals. The write operation cycle is selftimed and once initiated, will automatically time itself to completion.All major programming vendors offer worldwide s
41、upport for the Atmel microcontroller series. Please contact your local programming vendor for the appropriate software revision. Flash Programming and Verification Waveforms - High-voltage Mode (VPP = 12V)Flash Programming and Verification Waveforms - Low-voltage Mode (VPP = 5V)Flash Programming and
42、 Verification Characteristics TA = 0C to 70C, VCC = 5.0 10%Absolute Maximum Ratings*NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions bey
43、ond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.DC CharacteristicsTA = -40C to 85C, VCC = 5.0V 20% (unless otherwise noted)Notes: 1. Under steady state (non-transie
44、nt) conditions, IOL must be externally limited as follows:Maximum IOL per port pin: 10 mAMaximum IOL per 8-bit port: Port 0: 26 mAPorts 1, 2, 3: 15 mAMaximum total IOL for all output pins: 71 mAIf IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to si
45、nk current greater than the listed test conditions.2. Minimum VCC for Power-down is 2V.AC CharacteristicsUnder operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; load capacitance for all other outputs = 80 pF.External Program and Data Memory CharacteristicsExternal Progr
46、am Memory Read CycleExternal Data Memory Read CycleExternal Data Memory Write CycleExternal Clock Drive WaveformsExternal Clock DriveSerial Port Timing: Shift Register Mode Test Conditions(VCC = 5.0 V 20%; Load Capacitance = 80 pF)Shift Register Mode Timing WaveformsAC Testing Input/Output Waveforms
47、(1)Note: 1. AC Inputs during testing are driven at VCC - 0.5V for a logic 1 and 0.45V for a logic 0. Timing measurements are made at VIH min. for a logic 1 and VIL max. for a logic 0.Float Waveforms(1)Note: 1. For timing purposes, a port pin is no longer floating when a 100mV change from load voltag
48、e occurs. A port pin begins to float when 100mV change from the loaded VOH/VOL level occurs.AT89C51中文原文AT89C51是美国ATMEL公司生产的低电压，高性能CMOS8位单片机，片内含4k bytes的可反复擦写的只读程序存储器（PEROM）和128 bytes的随机存取数据存储器（RAM），器件采用ATMEL公司的高密度、非易失性存储技术生产，兼容标准MCS-51指令系统，片内置通用8位中央处理器（CPU）和Flash存储单元，功能强大AT89C51单片机可为您提供许多高性价比的应用场合，可灵活应用于各种控制领域。主要性能参数：与MCS-51产品指令系统完全兼容4k字节可重擦写Flash闪速存储器1000次擦写周期全静态操作：0Hz24MHz三级加密程序存储器1288字节内部RAM32个可编程IO口线2个16位定时计数器6个中断源可编程串行UART通道低功耗空闲和掉电模式功能特性概述：AT89C51 提供以下标准功能：4k 字节Flash 闪速存储器，128字节内部RAM，32 个IO 口线，两个16位定时计数器，一
