《毕业设计（论文）外文文献翻译3G移动终端基带信号处理器设计与实现.doc》由会员分享，可在线阅读，更多相关《毕业设计（论文）外文文献翻译3G移动终端基带信号处理器设计与实现.doc（11页珍藏版）》请在三一办公上搜索。
1、3G移动终端基带信号处理器设计与实现摘要：随着数字技术的进步，高速、超大规模集成电路广泛使用，3G移动终端基带信号处理系统正朝着灵活、高度集成化、模块化、通用化的方向发展。基带信号处理器是数字技术与通信技术相结合的产物，它能灵活处理数字基带信号，调制无线信号以便实现同通信网络系统前端基站的无线通信。文章设计了一种基于先进微处理器(ARM)、数字信号处理(DSP)和现场可编程门阵列(FPGA)体系结构的3G移动终端基带信号处理器。这种体系结构的优点在于当提供更能满足客户需求的先进处理器时，整个系统容易集成，而且可以通过软件方法方便地增加功能，而不必定制只读存储器(ROM)编码的新芯片。同时系统使
2、用软件实现联合检测和信号解码功能，通过软件更新轻松实现对系统的任何升级，无需硬件修改。 关键字：3G，信号处理Design and Realize of 3G Mobile Termination Baseband Signal ProcessorABSTRACT:Along with digital techniques progress, high speed, the ultra large scale integrated circuit widely uses, the 3G mobile termination baseband signal processing system t
3、oward nimble, integrated, modular, the universalized direction is developing highly. The baseband signal processor is the product which the digital technique and the communication unify, it can process the digital baseband signal nimbly, the modulation wireless signal in order to realize with the co
4、mmunication network system front end the base depot wireless communication. along with digital techniques progress, high speed, the ultra large scale integrated circuit widely uses, the 3G mobile termination baseband signal processing system toward nimble, integrated, modular, the universalized dire
5、ction is developing highly. The baseband signal processor is the product which the digital technique and the communication unify, it can process the digital baseband signal nimbly, the modulation wireless signal in order to realize with the communication network system front end the base depot wirel
6、ess communication. The article has designed one kind based on advanced microprocessor (ARM), digital signal processing (DSP) and scene programmable gate array (FPGA) the architecture 3G mobile termination baseband signal processor. This kind of architectures merit lies, when provides can meet the cu
7、stomer need the advanced processor, the overall system easy to integrate, moreover may increase the function conveniently through the software method, but does not need to have custom-made the non-erasable storage (ROM) code the new chip. Simultaneously the system use software realizes the union exa
8、mination and the signal decoding function, with ease realizes through the software update to systems any promotion, does not need the hardware to revise.KEYWORDS：3G,signal process1设计思路随着实时数字信号处理技术的发展，ARM、DSP和FPGA体系结构成为3G移动终端实现的主要方式。本文的设计通过ARM对目标及环境进行建模、运算，生成网络协议仿真数据库，应用DSP进行数据调度、运算和处理，最后形成所需的调幅、调相、调
9、频等控制字，通过FPGA控制收发器芯片产生射频模拟信号。利用数字芯片之间的通用性，ARM与DSP间的通信，不仅能实时处理接收和发送的数据，还可以适应不同移动网络的具体要求，同时方便加载新的程序。FPGA数字频率合成技术以其在频率捷变速度、相位连续性、相对带宽、高分辨率以及集成化等方面的优异性能，为 3G移动终端射频信号模拟的实现方式提供了选择。 2硬件实现本系统主要部分是ARM主控模块、DSP实时数据处理模块和FPGA信号生成模块。ARM主控模块实现物理层与协议栈的通信，接收高层的指令，执行相应的任务。如协议栈需要在某些子帧中的某个或几个上行时隙发送数据到核心网，在某些子帧中的某个或几个下行时
10、隙接收核心网的数据，这时把所有的指令和数据都存放在同步动态随机存储器(SDRAM)中，然后通知DSP去执行。DSP实时数据处理模块得到数据和命令后，首先处理发送数据，对数据进行信道编码调制、CRC附着、交织、扩频调制等，然后处理接收数据，如信道估计、去干扰、CRC校验、信道解码、解扩、唯特比解码等。FPGA为信号生成模块，管理26 M时钟，进行分频的任务，控制模拟基带(ABB)的自动发送功率控制(APC)、自动接收增益控制(AGC)、自动频率控制(AFC)等，同时也实时控制射频(RF)的工作。当DSP中的一些算法非常稳定后，可以用FPGA来实现这些算法，减少DSP的处理负担。2.1接口ARM与
11、DSP的数据交换是通过双口随机存储器(RAM)来实现的，起到上下行控制命令、参数和数据等缓存和交换的作用。这里收发双口RAM数据线的位数大小为16 bit，SDRAM 存储大小为128 M。硬件中断信号线8(INT8)与硬件中断信号线9(INT9)每5ms相互产生一次，等于TD-SCDMA空口信号的子帧中断，同时也可以作为ARM与DSP的控制命令、响应来实现ARM与DSP之间的通信。FPGA的主要的接口有data_out15:0接口，与数模转换器(A/D)接口和与RF接口。Data_out15:0接口用来输出FPGA运算的结果，与DSP的数据总线挂接在一起，在FPGA内部设置一个三态门，开门信
12、号就是 FPGA的片选信号CE。当CE不选通的时候，三态门输出为高阻状态，不会影响DSP的数据总线。在每一个样点间隔的时间内，FPGA运算出相关值的实部和虚部，将它们分别锁存在4个16 bit的锁存器中，并将与DSP相连的data_ready信号置高电平，表示数据已经准备好。DSP检测到data_ready为高后会进行读操作，用地址总线的高几位产生出片选信号将FPGA选通，通过地址总线的低两位A0、A1来选择4个锁存器的其中一个，依次读取实部和虚部两个32位数的高16位和低16位。FPGA内部会对DSP的读操作计数，确认数据分4次读出后，则将data_ready置低，直到下一次运算完毕后再抬高
13、。FPGA的频率、相位和幅度控制字的设置和控制信号的产生由TMS320C5510完成，FPGA可以看作是异步存储设备与TMS320C5510的外存储器接口 (EMIF)相连，EMIF采用32 bit总线。与数模转换器(A/D)接口的A/D一端连接ABB，另一端连接FPGA，传输要发送的数据和移动网络接收的数据。在与A/D的接口部分中，有 3个输入端RIF、PS和CLK。RIF用来串行输入A/D转换来的样点值；PS为帧同步信号，它在输入到FPGA后用来驱动FPGA内部的总体控制模块；Clock为移位时钟，它控制A/D与FPGA之间数据串行传输的移位。与RF接口主要是用来控制发送和接收RF芯片工作
14、。2.2主控模块主控模块负责控制和协调各种工作，ARM采用TI公司生产的开放式多媒体应用平台(OMAP)微处理器，通过集成锁相环倍频系统主频可以达到 66 MHz，最大外部存储空间可达256 MB，片上资源丰富，外围控制能力强性价比高。由它控制DSP模块接收网络发送的命令及参数，实现无线自由的协议通信。2.3实时数据处理模块实时数据处理模块1通过共享内存与ARM实现发送的命令、传输参数和数据，根据设定的移动终端工作状态，如Cell Search、随机接入过程(RA)、专用控制信道(DCCH)，及目标、环境的实时动态计算FPGA的控制字。同时也通过共享内存上报从网络接收的数据和信息传输给ARM;
15、通过锁存器向处理板提供控衰减控制信号实现睡眠，来达到省电。DSP采用TI公司C5000系列中的TMS320C5510，系统时钟达600 MHz，数据处理速率可以达到4 800 MIPS。提供32/16 bit主机口，具有两个独立的外部存储器接口，其中EMIF支持64 bit总线宽度。2.4 FPGA模块设计本文的设计采用Stratix系列芯片，内嵌多达10 Mbit的3种RAM块：512 bit容量的小型RAM、4 KB容量的标准RAM、512 KB的大容量RAM。FPGA模块具有True_LVDS电路，支持低电压差分信号(LVDS)、低电压正射极耦合逻辑(LVPECL)、准电流模式逻辑 (P
16、CML)和超传输模式(HyperTranport)差分I/O电气标准，且有高速通信接口。本设计提供了完整的时钟管理方案，具有层次化的结构和多达12个锁相环(PLL)。Stratix系列使用的开发软件是Altera公司提供的新一代开发软件Quartus II。该系列芯片的最大特色是内嵌硬件乘法器和乘加结构的可编程DSP模块，适用于实现高速信号处理。这种DSP模块是高性能的嵌入算术单元，它可以配置为硬件乘法器、加减法器、累加器和流水线寄存器。Stratix系列具有多达28个DSP模块，可配置为224个嵌入乘法器，可以为大数据吞吐量的应用提供灵活、高效和有价值的方案。这些DSP模块可以实现多种典型的
17、DSP功能，如有相关器、限冲击响应(FIR)滤波、快速傅立叶变换(FFT)功能和加密/解密功能等，其中相关器算法设计是各种其他算法实现的基础和基本组成部分。移动终端系统接收到的射频信号经过前端预处理后，送到A/D采样，然后通过串行方式输出样点值到FPGA2。每个样点值是用10 bit的二进制补码表示的，需先通过一个串/并转换器转化为宽度为10 bit的并行信号。首先样点值要进行的是希尔波特变换，希尔波特变换有多种实现方法，这里采用一个129阶的滤波器来实现，滤波器的抽头系数由 MATLAB函数Remez产生，得到与其正交的另一路信号;然后以这两路信号分别作为实部和虚部，与本地序列进行相关运算，
18、将相关值的实部和虚部送给 DSP做后续处理。这样，DSP才可以通过先对相关值求模，然后对模值出现的峰值的间隔、幅值和数目等信息进行判断和进一步处理，来确定是否捕捉到信号。2.5 PFGA与RF的接口、总线及时序控制设计为了增加信道容量、改善带宽效率，TD-SCDMA通过利用上行链路(反向链路)同步、软件无线电和智能天线的技术将时分双工(TDD)与 CDMA结合起来。TD-SCDMA要求手机的射频部分具有快速的切换时间、高的动态范围以及发送机和接收机部分的高线性度。MAX2410是一个完整正交发射器，它由一个正交调制器、可变增益IF和RF放大器组成。MAX2309是一种为基于CDMA的单频单模蜂
19、窝电话系统设计的IF接收机，其输入频率范围经过优化达到70 MHz300 MHz，在35 dB增益下达-33 dB，在-35 dB增益下达+1.7 dB。FPGA控制RF主要通过4个RF控制寄存器：A word寄存器、B word寄存器、C word寄存器和D word寄存器。3软件实现移动终端软件包括应用层软件、通信协议软件和物理层软件3部分。应用层软件LAY 4-7：包含人机界面(MMI)和系统应用层协议(S/W)部分，MMI为移动终端使用者接口，S/W类似移动终端的操作系统。通信协议软件LAY2-3：该部分软件较大，主要为通信协议，主要保证无线通信系统可以在各种状况顺畅互通。物理层软件L
20、AY 1：负责协调DSP、其他硬件和软件。物理层软件的设计将能实现节能的特性、多资源、多时隙的处理、数据包和对其他网络系统的监测。在设计物理层软件时的还要对相邻小区的监测，特别是当相邻小区间彼此还没有同步的时候。移动终端软件各个模块主要实现与硬件的对应关系如下：应用层软件LAY 4-7和通信协议软件LAY 2-3软件的实现主要是在ARM中实现，假如LAY 4-7需要一些特别高要求的应用时，可以再增加相应的硬件模块，而不影响原有的架构，如增加高要求多媒体的处理和播放;物理层软件LAY 1主要在DSP和FPGA中实现。在软件编程时ARM和DSP可以使用C语言来实现，使用的调试工具为CCS软件，当D
21、SP中有一些算法非常成熟后，移动通信对这块的实时性要求比较高时，应该用汇编语言来实现，在FPGA中可以用VHDL语言来实现。在编程是首先尽量定义好各个功能模块的任务，然后定义好各个功能模块的接口参数等，在可以不用全局变量的时候尽量不用。另一个主要挑战是在TD-SCDMA终端里实现联合检测算法，特别是关于算法的时间优化。DSP和FPGA之间的任务分配上要有一个合理协调的分工，这样能够最大限度的发挥这两个处理器的功能。在实际软件编程中，算法程序计算量大、编码延时过长，因此需要在保证质量的前提下对算法进行优化。在满足精度要求下,进一步将算法简化，粗化搜索范围来降低计算量;对于高级语言程序代码，用混合
22、汇编、去除嵌套循环等方法进行代码优化，提高代码效率。4 结束语该系统很好的实现了3G移动终端处理功能，但实际环境比仿真环境更复杂，需要给出解决办法，然后再验证。目前该方案实现了384 kb/s工作，使用3个时隙(每个时隙128 kb/s);实现了基于高速下行分组接入(HSDPA)技术提高数据速率，它类似于WCDMA和CDMA2000标准所提供的速率。开发的3G芯片组能够满足消费者对于改善性能和功能的要求，同时又保持了相同或更低的价格。Design and Realize of 3G Mobile Termination Baseband Signal Processor Along with
23、digital techniques progress, high speed, the ultra large scale integrated circuit widely uses, the 3G mobile termination baseband signal processing system toward nimble, integrated, modular, the universalized direction is developing highly. The baseband signal processor is the product which the digi
24、tal technique and the communication unify, it can process the digital baseband signal nimbly, the modulation wireless signal in order to realize with the communication network system front end the base depot wireless communication. along with digital techniques progress, high speed, the ultra large
25、scale integrated circuit widely uses, the 3G mobile termination baseband signal processing system toward nimble, integrated, modular, the universalized direction is developing highly. The baseband signal processor is the product which the digital technique and the communication unify, it can process
26、 the digital baseband signal nimbly, the modulation wireless signal in order to realize with the communication network system front end the base depot wireless communication. The article has designed one kind based on advanced microprocessor (ARM), digital signal processing (DSP) and scene programma
27、ble gate array (FPGA) the architecture 3G mobile termination baseband signal processor. This kind of architectures merit lies, when provides can meet the customer need the advanced processor, the overall system easy to integrate, moreover may increase the function conveniently through the software m
28、ethod, but does not need to have custom-made the non-erasable storage (ROM) code the new chip. Simultaneously the system use software realizes the union examination and the signal decoding function, with ease realizes through the software update to systems any promotion, does not need the hardware t
29、o revise.1 Design Mentality Along with the real-time digital signal processing technologys development, ARM, DSP and the FPGA architecture becomes the fundamental mode which the 3G mobile termination realizes. This article design carries on the modelling, the operation through ARM to the goal and th
30、e environment, the production network protocol simulation database, carries on the data dispatch, the operation and processing using DSP, finally forms control words and so on amplitude modulation which, phase modulation, frequency modulation needs, produces the radio frequency simulated signal thro
31、ugh the FPGA control transceiver chip. Using digital chip between versatility, ARM and DSP correspondence, not can only the real-time processing receive the data which and transmit, but may also adapt the different motion network specific request, simultaneously facilitates loads the new procedure.
32、The FPGA digit frequency synthesis technology take it in aspect and so on frequency agility speed, phase continuity, relative bandwidth, high resolution as well as integration outstanding performance, as the 3G mobile termination radio-frequency signal simulation realizes the way to provide the choi
33、ce.2 Hardware Realize This systems main part are the ARM master control module, the DSP real-time data processing module and FPGA signal production module. The ARM master control module realizes the physical level and the agreement stacks correspondence, receives the high-level instruction, carries
34、out the corresponding task. If the agreement stack needed in certain sub-frames some either several upward time slot transmission data to the core network, in certain sub-frames some or several downward time slot receive core networks data, by now deposits all instructions and the data in synchroniz
35、ed dynamic random-access memory (SDRAM), then informed DSP to carry out. After the DSP real-time data processing module obtains the data and the order, first processes the transmission data, carries on the channel coding modulation, CRC to the data to adhere to stick cohere, to interweave, the wide
36、frequency modulation and so on, then the processing receive data, like the channel estimated that disturbs, the CRC verification, the channel decoding, the despread, only especially compared to the decoding and so on. FPGA is the signal production module, manages 26 M clocks, carries on the frequenc
37、y division the duty, control simulation baseband (ABB) automatic transmission power control (APC), automatic reception gain control (AGC), automatic frequency control (AFC) and so on, simultaneously also real-time control radio frequency (RF) work. When in after DSP some algorithms are stable, may u
38、se FPGA to realize these algorithms, reduces DSP the processing burden. 2.1 Connection ARM and the DSP data exchange realizes through pair of mouth stochastic memory (RAM), namely Figure 1 SDRAM, plays ascending-descending buffers and the exchange and so on control command, parameter and data role.
39、Here receives and dispatches the pair of mouth RAM data line the figure size is 16 bit, the SDRAM memory size is 128 M. The hardware interrupt holding wire 8(INT8) produces mutually with hardware interrupt holding wire 9(INT9) every 5 ms one time, was equal to that the TD-SCDMA idle talk signal the
40、sub-frame interrupts, simultaneously may also as ARM and the DSP control command, the response realizes between ARM and the DSP correspondence.the FPGA main connection has the data_out15:0 connection, with d/a converter (A/D) connection and with the RF connection.the data_out15:0 connection uses for
41、 to output the FPGA operation the result, hangs with the DSP data bus meets in the same place, establishes a three states of matter gate in the FPGA interior, the enabling signal is FPGA selects patches or strips of land as worth saving for seed signal CE. When CE does not select, the three states o
42、f matter gate output is the high-resistance condition, will not affect DSP the data bus. In each sampling point gaps time, FPGA operates the correlative value the real part and the imaginary component, distinguishes the lock them to have 4 16 bit in the latches, and signal will set at the high level
43、 with DSP the connected data_ready, indicated that the data already prepared. DSP examines data_ready is Gao Houhui carries on reads the operation, produces with address buss high several selects patches or strips of land as worth saving for seed the signal to select FPGA, through address buss low t
44、wo A0, A1 chooses 4 latches, reads the real part and the imaginary component two 32 figures in turn high 16 and low 16. The FPGA interior will read the operation counting to DSP, confirmed after the data will be divided 4 read-out, will set at data_ready lowly, finished after the next operation rais
45、ed again. The FPGA frequency, the phase and the scope control words establishment and control signals production completes by TMS320C5510, FPGA may regard as is the asynchronous storage device and TMS320C5510 external memory connection (EMIF) is connected, EMIF uses 32 bit main lines. D/A converter
46、(A/D) connections A/D end connection ABB, another end connection FPGA, the transmission must transmit data and motion network receive data. With in a/D connection part, has 3 input end RIF, PS and CLK. RIF uses for the sampling point value which serial input A/D transforms; PS is the frame synchroni
47、zing signal, it in inputs uses for after FPGA to actuate the FPGA internal overall control module; Clock is shifts the clock, it controls between A/D and FPGA data serial transmission shifting. the RF connection is mainly uses for to control transmits and receives the RF chip work.2.2 Master Control
48、 Module the master control module is responsible to control and to be coordinated each kind of work, ARM uses the open style multimedia application platform (OMAP) microprocessor which TI Corporation produces, may achieve 66 MHz through the integrated phase-locked loop frequency multiplication syste
49、m basic frequency, the biggest exterior storage space may reach 256 MB, on the piece the fruitful in resources, the periphery control stubborn and unyielding person price scaled height of burst. Controls the DSP module receive network transmission by it the order and the parameter, realizes the wireless free agreement correspondence. 2.3 Real-time Data Processing Module real
