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1、CPU高效编程技术,核心系统数据库组 褚霸(余锋)2013-5-7,2,微处理器的核心技术,流水线处理运算器高速化RISC和CISC超标量执行乱序执行分支预测缓存多核心,了解处理器Nehalem E5620,长流水线=15级X86指令解释为微指令后乱序执行等待执行的微指令放在Reserveration Station多个ALU运算单元并发、乱序执行Reorder Buffer中实现串行化Instruction Retirement,Pipeline,示例：4级和8级的流水线,Intel的长流水线,Front End,读入x86指令，每个时钟周期16字节,x86指令解析为微指令（op）,微指令（
2、op）缓存,乱序执行-1,寄存器重命名,微指令进入保留站,分配临时寄存器,发射指令,各种运算,Load/Store,EU,EU,EU,乱序执行-2,存入临时寄存器,EU中计算结果,Load/Store,按指令顺序写出结果指令生效，真正写入内存和物理寄存器,触发具有数据依赖的指令执行,指令量化分析,取指令，每个16字节/cycleX86指令解析为微指令简单指令3条/cycle复杂指令1条/cycle保留站到EU的Port，总共6个P0，P1，P5到ALU单元P2，P3，P4到Load/Store单元Instruction Retirement，4条op/cycleDependency Chain
3、长度,指令优化,长流水线=15级Branch prediction miss性能损耗大减少Branch prediction miss率减少/消除conditional branchBit运算代替比较Comvg指令代替比较充分发挥Intel处理器乱序执行的能力避免指令间存在long dependency chain避免指令间隐性的依赖关系，例如对eflags的依赖,11,CPU内部各部件访问速度,12,充分利用寄存器,#define LZ4_COPYSTEP(s,d)A64(d)=A64(s);d+=8;s+=8;#define LZ4_COPYPACKET(s,d)LZ4_COPYSTEP(
4、s,d)#define LZ4_WILDCOPY(s,d,e)do LZ4_COPYPACKET(s,d)while(de);,13,位运算,int r;if(!(val32)r=4;else r=0;val=32;if(!(val16)r+=2;val=8;else val=24;r+=(!val);return r;,14,并行执行,*op+=*ref+;*op+=*ref+;*op+=*ref+;*op+=*ref+;,消除Conditional Branch,如何消除这个if语句if(a b)r=c;else r=d;,Bit运算版本1int mask=(a-b)31;r=(mask,
5、16,分支可能性提示,#define likely(expr)expect(expr)!=0,1)#define unlikely(expr)expect(expr)!=0,0)while likely(ipmatchlimit-(STEPSIZE-1),17,The Blocking Technique,18,The Blocking Technique,/Increasing memory usage improves compression ratio/Reduced memory usage can improve speed,due to cache effect/Default v
6、alue is 14,for 16KB,which nicely fits into Intel x86 L1 cache#define MEMORY_USAGE 14#define HASH_LOG(MEMORY_USAGE-2)#define HASHTABLESIZE(1 HASH_LOG)structrefTablesHTYPEhashTableHASHTABLESIZE;,19,memchr,magic_bits=(unsigned long int)0 x7efefefe=sizeof(longword)longword=*longword_ptr+charmask;if(long
7、word+magic_bits)&magic_bits)!=0),20,memchr续,const unsigned char*cp=(const unsigned char*)(longword_ptr-1);if(cp0=c)return(_ptr_t)cp;.if(cp7=c)return(_ptr_t),21,False sharing,22,对齐cacheline,typedef union GFAllctr_t gfa;char align_gfaERTS_ALC_CACHE_LINE_ALIGN_SIZE(sizeof(GFAllctr_t);ErtsAllocatorState
8、_t;char*states=erts_sys_alloc(0,+ERTS_CACHE_LINE_SIZE-1);states=(UWord)states),23,perf list,RAW HARDWARE EVENT DESCRIPTOR Even when an event is not available in a symbolic form within perf right now,it can be encoded in a per processor specific way.For instance For x86 CPUs NNN represents the raw re
9、gister encoding with the layout of IA32_PERFEVTSELx MSRs(see Intel(R)64 and IA-32 Architectures Software Developers Manual Volume 3B:System Programming Guide Figure 30-1 Layout of IA32_PERFEVTSELx MSRs)or AMDs PerfEvtSeln(see AMD64 Architecture Programmers Manual Volume 2:System Programming,Page 344,Figure 13-7 Performance Event-Select Register(PerfEvtSeln).,24,致谢,部分图片和代码来自鸣嵩 treelink比赛分享,25,多谢大家!Questions？新浪微博:淘宝褚霸,
