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1、Quantum Data-Overview,Mission StatementQuantum Data invents test instruments that help manufacturers bring next-generation audio,video,and control products to market faster and without interoperability problems.HistoryQuantum Data was founded in 1979 by Allen and Ann Jorgensen and has been at the le
2、ading edge of programmable video test generator technology since its inception.Over the years,the company has expanded the scope of its products to include other types of video test equipment.Youll find Quantum Data instruments in the Authorized Test Centers and design laboratories and production fa
3、cilities of major consumer electronics and information technology manufacturers throughout the world.,DisplayPort-Overview,GeneralA Video Electronics Standards Association(VESA)Standard.DisplayPort is a digital display interface standard(approved May 2006,current version 1.1 approved in April of 200
4、7).Defines a new license-free,royalty-free,state-of-the-art digital audio/video interconnect.Envisioned to replace both DVI and VGA interface.ApplicationsConnecting a computer and its display.Connects PCs,computer monitors,graphic cards.Can be used for internal display panels.TV displays.Projectors.
5、,DisplayPort-Architecture,DisplayPort Aux Channel Operation,Aux Channel providesDevice services(Content Protection&EDID)Device services over I2C emulationContent Protection(HDCP)EDIDLink services(link training)-Negotiates how DisplayPort devices communicate during link training,including:Number of L
6、anes(1,2,4)Lane Rate(1.62Gb/s or 2.7Gb/s)EqualizationLevelsAux Channel OperationAUX CH of DisplayPort is a half-duplex,bi-directional channelSource device is the master-AUX CH RequesterSink device is the slave-AUX CH Replier Source device initiates request transactionsSink device responds with a rep
7、ly transaction,DisplayPort Two Hot Plug Types,IRQ(interrupt request)pulse-0.5ms to 1msSource Device must read the link/sink status field of the DPCD and take corrective action.Hot plug event pulse-longer than 2msSource must read the receiver capability field and link/sink status field of the DPCD an
8、d take corrective action.,DisplayPort Test Requirements,Physical layer testing(main link and aux channel)Pattern testing Timings and test patternsLink layer testing Compliance and debug toolsHDCP testing Compliance and productionFunctional testing Signal analysis,EDID,etc.DDC/CI(MCCS),Quantum Datas
9、DisplayPort Test Solutions,Pattern testingSupports VESA timings up to 268MHz pixel rates(higher pixel rates supported soon).Over 300 test patterns with the ability to create custom patterns and bitmaps,animated images.ConfigurabilityOne(1),2&4 lane configurations with user-specified selection of eac
10、h to override link training.Lane rates of 1.62Gb/s&2.7Gb/s with user-specified selection of each to override link training.Standard configurability of 880 seriesLink layer compliance testing,forSources devices.Sinks devices.HTML reports provide pass/fail status and test details(coming soon).HDCP tes
11、tingCompliance Testing forSink devices approved by VTM(for VESA)as an authorized tool.Source devices(coming soon)and production.Production Testing forSink devices.HTML reports provide pass/fail status and test details(coming soon).Aux channel sniffer(coming soon)Logs link layer transactions such as
12、link trainingLogs HDCP,EDID&hot plug circuit transactionsMessaging interface supports for real time analysis or post test analysisEDID viewingOn connected displayHTML report,Pattern Testing of DisplayPort Sinks,Timings(formats)-Supports VESA timings up to 268MHz pixel rates(higher pixel rates/resolu
13、tions supported soon).Discrete Mode Timing(DMT)Coordinated Video Timing(CVT)Test patternsOver 300 standard static and animated test patternsImageShift animate any static test patternImport bitmaps and jpegsCreate custom images with graphics SDK API,880 Series DisplayPort Configurations,882E Series c
14、onfigurations supportedDisplayPort Tx cardDisplayPort Tx card with Rx card(coming soon)DisplayPort Tx card with ACA(aux channel sniffer)(Future)880 Series possible configurationsDisplayPort Tx card&Rx card&ACA card(aux channel sniffer)DisplayPort Tx card&Rx card&HDMI Tx,880 Series DP Programmability
15、,One(1),2 and 4 lane configurations with user-specified selection of each to override link training.Lane rates of 1.62Gb/s&2.7Gb/s with user-specified selection of each to override link training.Standard configurability offered by 880 series,including:Timing parameters such as vsync,hsync,resolution
16、,etc.Bit depths:6,8&10Sampling modes:4:4:4&4:2:2Color component gatingColorimetry:RGB or YCbCrComponent scaling ramp up/down color component values throughout entire range,DisplayPort Link Layer Testing,Link layer compliance testing of sink devices.Runs link layer compliance test(per spec)on sink de
17、vices in batch mode or individually through command line.The following tests are performed:,5.2.1.1 Read One Byte from Valid DPCD Address 5.2.1.2 Read Twelve Bytes from Valid DPCD Address5.2.1.3Write One Byte to Valid DPCD Address5.2.1.4Write Nine Bytes to Valid DPCD Addresses5.2.1.5 Write Nine Byte
18、s to Read-Only DPCD Address5.2.1.6 Write EDID Offset(One Byte I2C-Over-Aux Write)5.2.1.7 Read One EDID Byte(One Byte I2C-Over-Aux Read)5.2.1.8 EDID Read(1 Byte I2C-Over-Aux Segment Write,1 Byte I2C-Over-Aux Offset Write,128 Byte I2C-Over-Aux Read)5.2.1.9 Illegal Aux Request Syntax5.2.2 EDID Read5.3.
19、1.1 Successful Link Training at All Supported Lane Counts and Link Speeds5.3.1.2Successful Link Training with Request of Higher Differential Voltage Swing during Clock Recovery Sequence5.3.1.3 Successful Link Training to a Lower Link Rate Due To Clock Recovery Lock Failure During Clock Recovery Sequ
20、ence5.3.1.4 Successful Link Training with Request of a Change to Pre-Emphasis And/Or5.3.1.5 Successful Link Training at Lower Link Rate Due to Loss of Symbol Lock During Channel 5.3.1.6 Lane Count Reduction5.3.1.7Lane Count Increase5.3.2.1 IRQ_HPD Pulse Due to Loss of Symbol Lock and Clock Recovery
21、Lock5.3.2.2IRQ HPD Pulse Due to Loss of Inter-lane Alignment Lock5.4.1.1 Pixel data reconstruction5.4.1.2 Main Stream Data Unpacking and Unstuffing Least Packed TU5.4.1.3 Main Stream Data Unpacking and Unstuffing Most Packed TU5.4.2 Main Video Stream Format Change Handling,DisplayPort Link Layer Tes
22、ting,Link layer compliance testing for source devices.Runs link layer compliance test(per spec)on source devices in batch mode or individually through command line.The following tests are performed:,4.2.1.1 Source DUT Retry on No-Reply During Aux Read after Hot Plug Event4.2.1.2 Source Retry on Inva
23、lid Reply During Aux Read after Hot Plug Event4.2.2.1 EDID Read upon Hot Plug Event4.2.2.2 DPCD Receiver Capability Read upon Hot Plug Event4.2.2.3 EDID Read4.2.2.4 EDID Absence Detection4.2.2.5EDID Corruption Detection4.3.1.1 Successful Link Training Upon Hot Plug detect4.3.1.2Successful Link Train
24、ing at All Supported Lane Counts and Link Speeds4.3.1.3 Successful Link Training with Request of Higher Differential Voltage Swing during Clock Recovery Sequence4.3.1.4 Successful Link Training to a Lower Link Rate#1:Iterate at Maximum Voltage Swing4.3.1.5Successful Link Training to a Lower Link Rat
25、e#2:Iterate at Minimum Voltage Swing4.3.1.6 Successful Link Training with Request of a Higher Pre-emphasis Setting During Channel Equalization Sequence4.3.1.7 Successful Link Training at Lower Link Rate due to Loss of Symbol Lock During Channel Equalization Sequence4.3.1.8Unsuccessful Link Training
26、at Lower Link Rate#1:Iterate at Maximum Voltage Swing4.3.1.9 Unsuccessful Link Training at Lower Link Rate#2:Iterate at Minimum Voltage Swing4.3.1.10 Unsuccessful Link Training due to Failure in Channel Equalization Sequence4.3.1.11 Lane Count Reduction4.3.1.12 Lane Count Increase4.3.2.1 Successful
27、Link Re-training After IRQ HPD Pulse Due to Loss of Symbol Lock4.3.2.2Successful Link Re-training After IRQ HPD Pulse Due to Loss of Clock Recovery4.3.2.3Successful Link Re-training After IRQ HPD Pulse Due to Loss of Inter-lane4.3.2.4No link re-training required after IRQ HPD pulse4.4.1.1Pixel Data
28、Steering4.4.1.2Main Stream Data Packing and Stuffing Least Packed TU4.4.1.3 Main Stream Data Packing and Stuffing Most Packed TU4.4.2 Main Video Stream Format Change Handling,DisplayPort HDCP Testing,Compliance TestingSink devices approved by VTM(for VESA)as an authorized tool(coming soon)Source dev
29、icesProduction TestSink devices,DisplayPort HDCP Testing,Sample of HDCP Compliance Test report Summary Page.,DisplayPort HDCP Testing,Sample of HDCP Compliance Test report.Details Page,DisplayPort-Aux Channel Sniffer,Logs link layer transactions such as link trainingLogs device I2S transactions such
30、 as HDCP,EDID&hot plugMessaging interface support for real time analysis or post-test analysis,DisplayPort-Aux Channel Sniffer,Link transactions showing Link Training,S A M P L E O N L Y,DisplayPort-Aux Chan Sniffer(HDCP/EDID),Device transactions showingEDIDHDCP,S A M P L E O N L Y,DisplayPort EDID
31、Testing,EDID viewing/testingOn connected displayHTML report,Quantum Data DisplayPort Roadmap,Signal analysis for source tesingTiming measurements measures resolution(active/blanking)and vertical and horizontal sync ratesPixel error testing compares received frames vs reference frameImage capture display component valuesEDID EmulationEDID Editor supportDDC/CI(MCCS)Command GUIMessage logging through ACAAudioAudio signal generation,
