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1、浮点运算单元,浮点运算,Floating-Point NumbersIEEE 754 Floating-Point StandardFloating-Point Addition and SubtractionFloating-Point Multiplication,浮点数在计算机内的格式,浮点数:X=MS ES Em-1.E2 E1 M-1M-2.M-n,符号位 阶码位 尾数数码位 总位数,短浮点数:1 8 23 32,长浮点数:1 11 52 64,临时浮点数:1 15 64 80,IEEE 标准：阶码用移码，基为2；尾数用原码,浮点数的阶码的位数决定数的表示范围，尾数的位数决定数的有效
2、精度。,浮点数在计算机内的格式,IEEE 标准：尾数用原码,浮点数是数学中实数的子集合，由一个纯小数乘上一个指数值来组成。在计算机内，其纯小数部分被称为浮点数的尾数，对非 0 值的浮点数，要求尾数的绝对值必须=1/2，称满足这种表示要求的浮点数为规格化表示；把不满足这一表示要求的尾数，变成满足这一要求的尾数的操作过程，叫作浮点数的规格化处理，通过尾数移位和修改阶码实现。,浮点数在计算机内的格式,IEEE 标准：尾数用原码,按国际电子电气工程师协会规定的标准，浮点数的尾数要用原码表示，即符号位 Ms:0 表示正，1 表示负，且非 0 值尾数数值的最高位 M-1 必为 1,才能满足浮点数规格化表示
3、的要求；既然非 0 值浮点数的尾数数值最高位必定为 1，则在保存浮点数到内存前，通过尾数右移,强行把该位去掉,用同样多的尾数位就能多存一位二进制数，有利于提高数据表示精度，称这种处理方案使用了隐藏位技术。当然，在取回这样的浮点数到运算器执行运算时，必须先恢复该隐藏位。,Floating Point,浮点数在计算机内的格式,X=Ms Es Em-1.E1 E0 M-1 M-2.M-n,IEEE 标准：阶码用移码，基为2,按国际电子电气工程师协会规定的国际通用标准，浮点数的阶码用整数给出，并且要用移码表示，用作为以 2为底的指数的幂。既然该指数的底一定为 2，可以不必在浮点数的格式中明确表示出来，
4、只需给出阶码的幂值即可。移码表示只用于表示整数，只用在浮点数的阶码部分，其定义类似于整数的补码定义，差别在符号位。移码的符号位是 0 表示负，1 表示正，与补码的符号位正好相反，移码是指机器数在数轴上有个移位关系；移码的数值位则与补码的数值位完全相同。,浮点数格式：关于移码的知识,移码表示整数，用在浮点数的阶码部分。一位符号位和 n 位数值位组成的移码,其定义为；E移=2n+E-2n=E2n 表示范围：00000000 11111111,浮点数格式：关于移码的知识,一位符号位和 n 位数值位组成的移码,其定义为；E移=2n+E-2n=E2n 表示范围：00000000 11111111 负数
5、正数 机器数,0,移码只执行二数的加减运算与增 1、减 1 操作。加减运算时，符号位计算结果求反后,才是加减运算的正确符号位的值。注意:当用双符号位时，00代表负，01代表正，而不是11代表正,8 位的阶码能表示-128+127，当阶码为-128时，其补码表示为 00000000，该浮点数的绝对值2-128,人们规定此浮点数的值为零，若尾数不为 0 就清其为 0，并特称此值为机器零。,8 位移码表示的机器数为数的真值在数轴上向右平移了 128 个位置,-128,+127,Biased Exponent,Value of exponent=val(E)=E Bias(Bias is a cons
6、tant)8 bits for single precision E can be in the range 0 to 255 E=0 and E=255 are reserved for special use E=1 to 254 are used for normalized floating point numbers Bias=127(half of 254),val(E)=E 127 val(E=1)=126,val(E=127)=0,val(E=254)=127,Example of Exponent,Example of Normalized Mantissa,Biased E
7、xponent,Example of Floating Point,Largest Normalized Float,Smallest Normalized Float,Zero Infinity NaN,Denormalized numbers,Zero&Infinity,The value NaN(Not a Number)is used to represent a value that does not represent a real number.NaN is a special value represented with maximum E and F 0Result from
8、 exceptional situations,such as 0/0 or sqrt(negative)Operation on a NaN results is NaN:Op(X,NaN)=NaNQNaN denote indeterminate operations,SNaN denote invalid operations,NaN,FP Add,FP Add,Floating Point Subtraction Example,Floating Point Subtraction Example,Extra bits,Guard bit,Extra bit,Rounding Mode
9、,nearest In this mode,the inexact results are rounded to the nearer of the two possible result values.If the neither possibility is nearer,then the even alternative is chosen.This form of rounding is also called round to even。“Even”when least significant bit is 0ValueBinary RoundedActionRounded Valu
10、e2 3/3210.00011210.002(1/2up)2 1/42 7/810.11100211.002(1/2up)32 5/810.10100210.102(1/2down)2 1/2,Rounding Mode,Steps in Addition/Subtraction of Floating-Point Numbers,Step 1:Calculate difference d of the two exponents-d=|E1-E2|Step 2:Shift significand of smaller number by d-base positions to the rig
11、htStep 3:Add aligned significands and set exponent of result to exponent of larger operandStep 4:Normalize resultant significand and adjust exponent if necessaryStep 5:Round resultant significand and adjust exponent if necessary,Addition/Subtraction Structure,Addition/Subtraction,E1E2-,Exponent of l
12、arger number not decreased-this will result in a larger significand adder required.,Addition-resultant significand M(sum of two aligned significands)is in range 1/M 1-a postnormalization step-shifting significand to the right to yield M3 and increasing exponent by one-is required(an exponent overflo
13、w may occur),Addition/Subtraction Normalization,Subtraction-Resultant significand M is in range 0|M|1-postnormalization step-shifting significand to left and decreasing exponent-is required if M1/(an exponent underflow may occur)In extreme cases,the postnormalization step may require a shift left op
14、eration over all bits in significand,yielding a zero result.,Effective Addition/Subtraction,Distinguish between effective addition and effective subtraction Depends on sign bits of operands and instruction executedEffective addition:Calculate exponent difference to determine alignment shift Shift si
15、gnificand of smaller operand,add aligned significandsThe result can overflow by at most one bit positionLong post-normalization shift not neededSingle bit overflow can be detected and,if found,a 1-bit normalization is performed using a multiplexor,Eliminate Increment in Rounding,Significand adder de
16、signed to produce two simultaneous results-sum and sum+1Called compound adder;can be implemented in various ways(e.g.,carry-look-ahead or conditional sum)Round-to-nearest-even-use rounding bits to determine which of the two should be selected These two are sufficient even if a single bit overflow oc
17、curs In case of overflow,1 is added in R position(instead of LSB position),and since R=1 if rounding needed,a carry will propagate to LSB to generate correct sum+1 Directed roundings-R not necessarily 1-sum+2 may be needed,Effective Subtraction,Massive cancellation of most significant bits may occur
18、-resulting in lengthy postnormalization Happens only when exponents of operands are close(difference 1)-pre-alignment can be eliminatedTwo separate procedures-(1)exponents are close(difference 1)-only a postnormalization shift may be needed(2)exponents are far(difference1)-only a pre-alignment shift
19、 may be needed,CLOSE Case,Exponent difference predicted based on two least significant bits of operands-allows subtraction of significands to start as soon as possibleIf 0-subtract executed with no alignmentIf 1-significand of smaller operand is shifted once to the right(using a multiplexor)and then
20、 subtracted from other significand In parallel-true exponent difference calculated If 1-procedure aborted and FAR procedure followedIf 1-CLOSE procedure continuedIn parallel with subtraction-number of leading zeros predicted to determine number of shift positions in postnormalization,CLOSE Case-Norm
21、alization and Rounding,Next-normalization of significand and corresponding exponent adjustment Last-rounding-precomputing sum,sum+1-selecting the one which is properly rounded-negation of result may be necessary Result of subtraction usually positive-negation not requiredOnly when exponents equal-re
22、sult of significand subtraction may be negative(in twos complement)-requiring a negation stepNegation and rounding steps-mutually exclusive,FAR Case,First-exponent difference calculated Next-significand of smaller operand shifted to right for alignment Shifted-out bits used to set sticky bitSmaller
23、significand subtracted from larger-result either normalized.Last step-rounding,Leading Zeros Prediction Circuit,Predict position of leading non-zero bit in result of subtract before subtraction is completed Allowing to execute postnormalization shift immediately following subtractionExamine bits of
24、operands(of subtract)in a serial fashion,starting with most significant bits to determine position of first 1 This serial operation can be accelerated using a parallel scheme similar to carry-look-ahead,Leading Zeros Prediction Circuit,Predict position of leading non-zero bit in result of subtract b
25、efore subtraction is completed Allowing to execute postnormalization shift immediately following subtractionExamine bits of operands(of subtract)in a serial fashion,starting with most significant bits to determine position of first 1 This serial operation can be accelerated using a parallel scheme s
26、imilar to carry-look-ahead,Alternative Prediction of Leading 1,Generate in parallel intermediate bits ei-ei=1 ifai=bi and ai-1 and bi-1 allow propagation of expected carry(at least one is 1)Subtract executed by forming ones complement of subtrahend and forcing carry into least significant position-c
27、arry expected,ei=(ai bi)(ai-1+bi-1)-ei=1 if carry allowed to propagate to position i If forced carry propagates to position i-i-th bit of correct result will also be 1If not-correct result will have a 1 in position i-1 insteadPosition of leading 1-either same as ei or one to the rightCount number of leading zeros in ei-provide count to barrel shifter for postnormalization-at most one bit correction shift(left)needed,
