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1、组合逻辑电路,Chapter6 Combinational Logic Design Practices,Chapter Outline,Documentation StandardsDigital Circuit Timing and Propagation delayCombinational Logic Design Structures:-Decoders-Encoders-Three-State Buffers-Multiplexers-EXCLUSIVE OR Gates and Parity Circuits-Comparators-Adders/Subtractors-Arit
2、hmetic Logic Units(ALUs),6.1 Documentation Standard(文档标准),Documentation of a digital system should provide the necessary information for building,testing,operating,and maintaining the system.Specification:Description of Interface and Function(说明书：接口及功能描述)Block Diagram:Systems Major Function Module a
3、nd their Basic Interconnections(方框图：主要功能模块及其互联 P345图6-1)Schematic Diagram:showing all the components,their types,and all interconnections(原理图（P360图6-17）),Block Diagram,Schematic Diagram,Hierarchichal schematic structure,Documentation Standard(文档标准),Timing Diagram:showing the logic signals as a funct
4、ion of time(定时图（P363图6-19）)Structure Logic Device Description:showing the operation of the structures(结构化逻辑器件描述)Circuit Description:Explains how the circuit works internally.(电路描述：解释电路内部如何工作),“Hierarchical Design”,Gate Symbols(门的符号),DeMorgan equivalent symbols(等效门符号（摩根定理）),Which symbol to use?,depen
5、ds on signal names and active levels.,Signal Names and Active Levels(信号名和有效电平),Signal name:a descriptive alphanumeric label for each input/output signal.In real system,well-chosen names convey information to readersEach signal name should have an active-level associated with it.(有效电平)Active High（高电平
6、有效）Active Low（低电平有效）,Signal Name and Active Levels(信号名和有效电平),The signal is asserted when it is in its active level and negated(or deasserted)when its not in its active level.An Inversion Bubble to Indicate an Active-Low Pin(有反相圈的引脚 表示低电平有效)Active low signal has a suffix of _L as part of the variable
7、 name.,Signal Name and Active Levels(信号名和有效电平),AND,OR,and a large-scale logic element have active-high inputs and outputs,The same elements with active-low inputs and outputs,Given Logic Function as Occurring inside that symbolic outline.(给定逻辑功能只在符号框的内部发生),Bubble-to-Bubble Logic Design(“圈到圈”的逻辑设计),P
8、urpose:To make it easy to understand the function of the Logic circuit by choosing appropriate logic symbols and signal names including active-level designators.,Bubble-to-Bubble Logic Design(“圈到圈”的逻辑设计),6.2 Circuit Timing(电路定时),Propagation Delay(传播延迟),-A Signal Path as the Time that it takes for a
9、Change at the Input to Produce a Change at the Output of the Path(信号通路输入端的变化引起输出端变化所需的时间),tpHL and tpLH Maybe Different,Propagation Delay,Timing Analysis:Worst-Case Delay(定时分析：取最坏情况延迟),P366 表6-2,6.2 Circuit Timing(电路定时),Timing Diagram定时图（时序图）,6.2 Circuit Timing(电路定时),Causality and Propagation Delay(
10、因果性和传播延迟）,6.2 Circuit Timing(电路定时),Timing Diagram定时图（时序图）,Minimum and Maximum Delay(最小和最大延迟）,6.2 Circuit Timing(电路定时),Certain and Uncertain Transitions(确切的和不确切的转换）,Commonly Used MSI Combinational Logic Device,Decoders(译码器)Encoders(编码器)Multiplexers(多路复用器)Parity Circuits(奇偶校验)Comparators(比较器)Adders(加法
11、器),Decoder and Encoder(译码器和编码器),Multiple-Input,Multiple-Output Logic Circuit(多输入、多输出电路),Enable Inputs must be Asserted to perform Normal Mapping Function(使能输入有效才能实现正常映射功能),Input Code Word,Output Code Word,Decoder（译码器）Normally Output Code has More bits than its Input Code(一般来说，输出编码比输入编码位数多)Encoder（编码
12、器）Output Code has Fewer bits than its Input Code called an Encoder(输出编码比输入编码位数少，则常称为编码器),Decoder and Encoder(译码器和编码器),Most Commonly Used Case,Decoder（译码器）,Encoder（编码器）,(1-out-of 2n),6.4 Decoder（译码器）,Binary Decoder(二进制译码器)1.2-to-4 Decoder,0 X X 0 0 0 0 1 0 0 0 0 0 1 1 0 1 0 0 1 0 1 1 0 0 1 0 0 1 1 1
13、1 0 0 0,Y0=EN(I1 I2)Y1=EN(I1 I2)Y2=EN(I1 I2)Y3=EN(I1 I2),Yi=EN mi,Decoder（译码器）,2-to-4 Decoder,The 74x139 Dual 2-to-4 Decoder(双2-4译码器74x139),1 X X 1 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 1,Logic Symbols for Large-Scale Element,0 0 0 0 0 0 0 10 0 0 0 0 0 1 00 0 0 0 0 1 0 00 0 0 0
14、 1 0 0 00 0 0 1 0 0 0 00 0 1 0 0 0 0 00 1 0 0 0 0 0 01 0 0 0 0 0 0 0,Yi=EN mi,1 1 1 1 1 1 1 01 1 1 1 1 1 0 11 1 1 1 1 0 1 11 1 1 1 0 1 1 11 1 1 0 1 1 1 11 1 0 1 1 1 1 11 0 1 1 1 1 1 10 1 1 1 1 1 1 1,Decoder（译码器）,2.3-to-8 Decoder,The 74x138 3-to-8 Decoder(3-8译码器74x138),EN=G1 G2A G2B=G1 G2A_L G2B_L,Yi
15、=EN mi,Yi_L=Yi=(EN mi),ABC,G1G2AG2B,Y0Y1Y2Y3Y4Y5Y6Y7,74x138,Logic diagram for the 74x138,用74x138设计4-16译码器,Cascading Binary Decoders,思路：16个输出需要 片74x138？,任何时刻只有一片在工作。4个输入中，哪些位控制片选哪些位控制输入,Consider:How to make a 5-to-32 Decoder with 3-to-8 Decoder?32个输出需要多少片74x138？控制任何时刻只有一片工作 利用使能端5个输入的低3位控制输入5个输入的高2位控
16、制片选 利用 2-4 译码器,P391 图6-37,Use decoder and Gates to realize logic function,F=(X,Y,Z)(0,3,6,7)=(X,Y,Z)(1,2,4,5),Binary decoder：Yi=EN mi Enable inputs are asserted:Yi=mi Yi_L=Yi=mi=Mi,Use decoder and Gates to realize logic function,ZYX,F=(X,Y,Z)(0,3,6,7),当使能端有效时Yi=mi,Use decoder and Gates to realize lo
17、gic function,ZYX,F=(X,Y,Z)(0,3,6,7),=M1 M2 M4 M5,=m1 m2 m4 m5,F=(X,Y,Z)(1,2,4,5),ZYX,BCD Decoder(二十进制译码器),Inputs:4-bit BCD codeOutputs:1-out-of 10 Code,多余的6个状态如何处理？,输出均无效：拒绝“翻译”,作为任意项处理 电路内部结构简单,二-十进制译码器,Dont care,Seven-Segment Decoders(七段显示译码器),Normally use：Light-Emitting Diodes（LED,半导体数码管）Liquid-C
18、rystal Display（LCD,液晶数码管）,LED显示器件,LCD显示器件,LED,点阵型显示器,笔划段型显示器,Input code:4-bit BCD 输入信号：BCD码（用A3A2A1A0表示）Output Code:Seven-Segment Code输出：七段码（的驱动信号）a g 1-On，0-Off,1111110,1101101,0011111,Seven-Segment Decoders,74LS48显示字型与输入的对应关系,七段显示译码器的真值表,Karnaugh Maps for BCD-Seven-Segment Decoder(BCD-七段显示译码器的卡诺图)
19、,Karnaugh Maps for BCD-Seven-Segment Decoder(BCD-七段显示译码器的卡诺图),Karnaugh Maps for BCD-Seven-Segment Decoder(BCD-七段显示译码器的卡诺图),Karnaugh Maps for BCD-Seven-Segment Decoder(BCD-七段显示译码器的卡诺图),Design BCD-Seven-Segment Decoder,逻辑抽象，得到真值表输入信号：BCD码（A3A2A1A0）输出：七段码（的驱动信号）a g 1 表示亮，0 表示灭选择器件类型采用基本门电路实现，利用卡诺图化简采用二
20、进制译码器实现，变换为标准和形式电路处理，得到电路图,6.5 Encoder（编码器）,1 0 0 0 0 0 0 0 0 0 00 1 0 0 0 0 0 0 0 0 10 0 1 0 0 0 0 0 0 1 00 0 0 1 0 0 0 0 0 1 10 0 0 0 1 0 0 0 1 0 00 0 0 0 0 1 0 0 1 0 10 0 0 0 0 0 1 0 1 1 00 0 0 0 0 0 0 1 1 1 1,2nInputs,nOutputs,Guarantee:-one and only one input will be asserted at a time(任何时刻只有一个
21、输入端有效。),Encoder（编码器）,Truth Table for a 8-to-3 Encoder,this is the exact opposite of a decoder,A0=I1+I3+I5+I7,A1=I2+I3+I6+I7,A2=I4+I5+I6+I7,How to deal with multiple requests?-more than One Inputs are asserted,Priority（优先级）,Encoder（编码器）,Truth Table for a 8-to-3 Encoder,In order to write logic equatio
22、ns for the priority encoders outputswe first define eight intermediate variables H0-H7,Highest-Priority(数大优先),Priority Encoder(优先编码器),H7=I7H6=I6 I7H5=I5 I6 I7H0=I0 I1 I2 I6 I7,In order to write logic equations for the priority encoders outputswe first define eight intermediate variables H0-H7,Highes
23、t-Priority(数大优先),Priority Encoder(优先编码器),A2=H4+H5+H6+H7A1=H2+H3+H6+H7A0=H1+H3+H5+H7,The IDLE Output is asserted if No Inputs are asserted.IDLE=I0 I1 I6 I7,The 74x148 Priority Encoder,2个74x148级联为16-4优先编码器,输入：由864，需8片74x148每片优先级不同（怎样实现？）保证高位无输入时，次高位才工作 高位芯片的EO端接次高位芯片的EI端,用8-3优先编码器74x148级联为64-6优先编码器,片间
24、优先级的编码 利用第9片74x148 每片的GS端接到第9片的输入端 第9片的输出作为高3位（RA5RA3）,片内优先级片间优先级,输出：6位,8片输出A2A0通过或门作为最终输出的低3位RA2RA0,分析判定优先级电路：（利用74x148）8个_电平有效输入I0_LI7_L，_的优先级最高 地址输出A2A0，_电平有效 若输出AVALID高电平有效，则表示_,A2A1A0,AVALID,低,I0_L,至少有一个输入有效,高,P514 题6.53,设计优先级电路：（利用74x148）8个输入I0I7高电平有效，I7优先级最高 地址输出A2A0，高电平有效 如果没有输入有效，输出IDLE有效,P
25、514 题6.52,6.6 Three-State Devices(三态器件),Three-State Buffer(Three-State Driver)三态缓冲器（三态驱动器）Three States:Active High(1)，Active Low(0),Hi-Z,Various three-state buffers,Three-State Devices,Three-State Device allow Multiple Sources to Share a Single“Party Line”As long as Only One device“talk”on the Line
26、at a time（三态器件允许多个信号源共享单个“同线”，条件是每次只有一个器件工作）(Figure 6-52)Typical Three-State Devices are Designed So that they go into the Hi-Z state Faster than they come out of the Hi-Z state.（对典型的三态器件，进入高阻态比离开高阻态的时间快）,fighting（冲突）,利用使能端进行时序控制,三态器件允许信号共享单个“同线”（party line）,典型的三态器件，进入高阻态比离开高阻态快,Standard SSI and MSI
27、 Three-State Buffer(标准SSI和MSI三态缓冲器),The 74x541 Octal three-state buffer,Notation of Data Bus（数据总线的表示法）,Transfer Data in Either Directions By Using Three-State Transceiver(利用三态缓冲器实现数据双向传送),Bus Transceiver(总线收发),6.7 Multiplexer（多路复用器）,Digital Switch,Multi-Switch,Data Selector(又称数据开关、多路开关、数据选择器)（缩写：MUX
28、）Under Select Controlling Signals,Select One of the Multi-Inputs to the Output(在选择控制信号的作用下，从多个输入数据中选择其中一个作为输出。),Multiplexer,Enable 使能,Select 选择,数据输出（1位）,8-Input,1-bit Multiplexer,8-Input,1-bit Multiplexer,How to get a logic equation for a MUX output?,2-Input,4-bit Multiplexer,4-Input,2-bit Multiplex
29、er,Truth Table for a 74x153,双4选1,Expanding Multiplexers(扩展多路复用器),Expanding Bit(扩展位)How to Realize 8-Input,16-bit Multiplexer?From 8-Input,1-bit to 8-Input,16-bit(由8输入1位8输入16位)Need 16 74x151,Each Chip Process 1-bit(需要16片74x151，每片处理输入输出中的1位),Expanding Multiplexers(扩展多路复用器),Expanding Bit(扩展位)Select-Inp
30、uts Connect to C,B,A of Each Chip(选择端连接到每片的C,B,A)Note:The Fanout Ability of Select field(注意：选择端的扇出能力)（驱动16个负载）,Expanding Inputs(扩展数据输入端的数目)How to realize 32-Input,1-bit Multiplexer(如何实现32输入，1位多路复用器？)Inputs from 8 to 32,Need 4 chips(数据输入由832，需4片)How to control Select Inputs-By High bit plus Low bit.(
31、如何控制选择输入端？分为：高位低位),Expanding Multiplexers(扩展多路复用器),Expanding Inputs(扩展数据输入端的数目)如何实现32输入，1位多路复用器？High Bits plus Decoder as Select(高位译码器进行片选)Low Bits Connect to C,B,A of each Chip(低位接到每片的C,B,A)Output Using OR Gate(4片输出用或门得最终输出),Expanding Multiplexers(扩展多路复用器),Dual 4-to-1 Multiplexer to 8-to-1 Multiple
32、xer,Use MUX to design combinational circuit,When enable input is asserted，,Canonic sum,CBA,F,实现逻辑函数 F=(A,B,C)(0,1,3,7),Ex：Use 4-to-1 MUX to realize:,解：观察逻辑逻辑函数表达式，每个与项都包含了变量A和C，因此用A、C作数据选择器的选择输入端，变换逻辑函数表达式如下,对比：四选一MUX表达式,令A1=A，A0=C,EN=0，D0=0，D1=D，D2=B，D3=B,1,0,Z,Z,Z,Z,Z,0,降维：由4维3维,说明：用具有n位地址输入端的多路复用
33、器，可以产生任何形式的输入变量数不大于n+1的组合逻辑函数。,Use MUX to realize logic function Karnugh maps,1、将卡诺图画成与数据选择器相适应的形式。也就是说，所使用的数据选择器有几个地址选择输入端，逻辑函数卡诺图的某一边就应有几个变量，且就将这几个变量作为数据选择器的地址选择码 2、将要实现的逻辑函数填入卡诺图并在卡诺图上画圈。顺着地址选择码的方向画圈 3、求输入数据端的逻辑函数表达式。4、根据选择端和输入数据端的逻辑函数表达式，画出用数据选择器实现的电路。,Ex.Use 4-to-1 MUX 74x153 and 8-to-1 MUX 74x
34、151 to realize the function respectively.,F(A,B,C,D)=m(0,1,5,6,7,9,10,13,15)+(4,8,11,12),Solution 1:4-to-1 MUX 74x153,D0=C D1=1D2=1 D3=D,Solution 2:8-to-1 MUX 74x151,Demultiplexer（多路分配器）,Route the bus data to one of m destinations(把输入数据送到m个目的地之一),A binary decoder with an enable input can be used as
35、a demultiplexer(利用带使能端的二进制译码器作为多路分配器),Enable input is connected to the data line(利用使能端作为数据输入端),Can you tell the circuit function？,6.8 Parity Circuit(奇偶校验电路),Odd-Parity Circuit（奇校验电路）Output is 1 if an odd number of its inputs are 1.(如果输入有奇数个1，则输出为1。)Even-Parity Circuit（偶校验电路）Output is 1 if an even nu
36、mber of its inputs are 1.(如果输入有偶数个1，则输出为1。)回顾：用什么可以判断1的个数？,Parity Circuit,Output of odd-parity circuit is inverted,we get an even-parity circuit.(奇校验电路的输出反相就得到偶校验电路),N XOR gates may be cascaded to form a circuit with n+1 inputs and a single output.(n个异或门级联，形成具有n+1个输入和单一输出的电路),Review of XOR AND XNOR,
37、AB=(AB)AB=AB AB=AB,Any two signals(inputs or output)of an XOR or XNOR gate may be complemented without changing the resulting logic function.(Figure 6-69)(对于异或门、同或门的任何2个信号（输入或输出）都可以取反，而不改变结果的逻辑功能),F=AB,F=AB,F=(AB),F=(AB),Cascading XOR Gates(Figure 6-70）,9-bit Odd/Even Parity Generator 74x280(9位奇偶校验发
38、生器74x280),Figure 6-71,Parity-Checking Applications,用于检测代码在传输和存储过程中是否出现差错,ERROR,发端保证有偶数个1,收端 ODD 有效表示出错,6.9 Comparator（比较器）,Compare two Binary words and indicate whether they are equalComparator:Check if two Binary words are equal(等值比较器：检验数值是否相等)Magnitude Comparator:Compare their magnitude(Greater th
39、an,Equal,Less than)(数值比较器：比较数值的大小（,=,）),Comparator,How to build a 1-bit Comparator?(如何构造1位等值比较器？)Use XOR(XNOR),给出足够的异或门和宽度足够的或门，可以搭建任意输入位数的等值比较器。,How to Build a N-bit Comparator?,Iterative circuit（迭代电路）,Iterative：重复的,反复的,数迭代的,Boundary inputs 边界输入,Boundary outputs边界输出,Cascading output级联输出,An Iterativ
40、e Comparator,1,每位串行比较,迭代的方法可能节省费用，但速度慢,Figure 6-77,1-Bit Magnitude Comparator(一位数值比较器),AB（A=1,B=0）则 AB=1 可作为输出信号 AB（A=0,B=1）则 AB=1 可作为输出信号 A=B，则AB=1，可作为输出信号,输出低电平有效,EQ_L=AB+AB=AB=(AB),LT:Less ThanEQ:EqualGT:Greater Than,n-Bit Magnitude Comparator(多位数值比较器),A(A3A2A1A0)和 B(B3B2B1B0)自高而低逐位比较,EQ=(A3B3)(A
41、2B2)(A1B1)(A0B0),GT=(A3B3),LT=EQ GT=(EQ+GT),或(A3=B3)(A2=B2)(A1B1),或(A3=B3)(A2=B2)(A1=B1)(A0B0),或(A3=B3)(A2B2),74x85,4-Bit Comparator 74x85(4位比较器74x85),通常低位的输出接高位的输入,AEQBOUT=(A=B)AEQBIN,AGTBOUT=(AB)+(A=B)AGTBIN,Serial Expanding Comparators(比较器的串行扩展),XY,3片74x85构成12位比较器,8-bit comparator 74x682,问题1：怎样表示
42、以下输出？active-high：P DIFF Q active-high：P EQ Q active-high：P GE Q active-high：P LT Q（P463 图6-81）,问题2：能否扩展？,注意：没有级联输入端,P464 Figure 6-82,3片74x682构成24位比较器,Parallel Expanding Comparators(比较器的并行扩展),Applications of comparator对产品分装的方框图,产品在传送带上输送，经过光电变换，将获得的与产品个数一致的电脉冲放大整形，加到计数器上计数。当计数器计得的数目与设定值相等时，比较器输出高电平，用
43、这个高电平去控制相应的装置，使产品分箱。,6.10 Adder(加法器),Half Adder and Full Adder（半加器和全加器）,Sum(相加的和):S=AB+AB=A BCarry(向高位的进位)：CO=AB,Truth Table of Half Adder,S=X Y CI,XY,XCI,CO=+,YCI,=XY+(X+Y)CI,Adder,Half Adder and Full Adder（半加器和全加器）,Truth Table of Full Adder,Ripple Adder(串行进位加法器),(缺点：运算速度慢，有较大的传输延迟)tADD=tXYCout+(n-
44、2)*tCinCout+tCinS,=0,回顾：串行比较器,Improve Speed:Parallel Adder(提高速度：并行加法器),Disadvantage:Slow,More Propagation Delay,Ripple Adder,BoundaryInputs,BoundaryOutputs,Carry-Lookahead Adder(先行进位加法器),Carry lookahead(先行进位法)：第 i 位的进位输入信号可以由该位以前的各位状态决定。,Ci+1=(XiYi)+(Xi+Yi)Ci,=Gi+Pi Ci,先行进位法：第 i 位的进位输入信号可以由该位以前的各位状态
45、决定。,C0=0,Ci+1=Gi+Pi Ci,C0=0 C1=G0+P0C0 C2=G1+P1C1=G1+P1(G0+P0C0)=G1+P1G0+P1P0C0 Cn=Gn+PnCn,展开为“与-或”式：三级延迟,MSI加法器74x283P480 图6-87,Carry-Lookahead Adder,MSI Arithmetic and Logic Units(ALU,MSI 算术逻辑单元),Perform any of a number of different arithmetic and logical operations on a pair of b-bit operands.(对2个b位的操作数进行若干不同的算术和逻辑运算),输出数据,0算术/1逻辑,选择特定操作,Table 6-70,第六章 小结,文档标准和电路定时（了解）常用的中规模集成电路（MSI）编码器、译码器、多路复用器、奇偶校验、比较器、加法器、三态器件掌握基本功能，级联的方法综合应用：利用基本MSI器件作为基本单元设计更复杂的组合逻辑电路,Homework,6.96.13 6.165.20(a)(c)(e)(f)6.216.246.29,6.386.436.516.526.53思考：6.39*6.77*,
