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1、2023/9/11,Chapter 9 Memory、CPLD and FPGA,本章只要求存储器中的ROM及其用于组合逻辑电路的设计,2023/9/11,chapter 9,2023/9/11,chapter 9,memory,ROM(read-only memory),RAM(random-access memory),Non-volatile while powered down,Volatile while powered down,Often be used store firmware or initial program of the computer,Data exchange
2、 and storing temporarily in CPU or other microprocessor,memory：store bits in a structured way,2023/9/11,chapter 9,9.1 Read-Only Memory(ROM),1.basic strcture,2nb ROM,n-bit address input,b-bit data output,sketch map of RAM,2023/9/11,chapter 9,2.Internal ROM structure,Row(address)decoder,A0,A1,An-1,sto
3、rage array（Mb）,D0,Db-1,output circuit,0,1,M,address input,Data output,2023/9/11,chapter 9,address decoder,输出电路,address input,Data output,has diode:store 1no diode:store 0,84 ROM structure,2023/9/11,chapter 9,3.Two-dimensional decoding,1281ROM,00000000001111,00100000011111,11100001111111,地址,2023/9/11
4、,chapter 9,MOS transistors as storage elements,2023/9/11,chapter 9,mercial ROM types,mask-programmable ROM,array connections are programmed during semiconductor manufacture using a mask.very fast.very dense.expensive,2-4 week turn-around,low powerProgrammable ROM(PROM),fuses to program once in the f
5、ield,use PROM programmer,inexpensive,2023/9/11,chapter 9,EPROM（Erasable PROM）,fuses implemented using floating-gate MOS transistors to program 10k100k times in the field,erased by flooding with UV light.E2PROM（Electrically EPROM）,byte-program,individual stored bits may be erased electrically.flash E
6、2PROM,a specific type of E2PROM that is erased and programmed in large blocks,2023/9/11,chapter 9,floating-gate MOS storage elements,erased by UV light,2023/9/11,chapter 9,按照数据的输入/输出分为串行EEPROM和并行EEPROM。串行EEPROM：在读写数据时，输入/输出时通过2线、3线、4线或SPI总线等接口方式进行的。并行EEPROM：数据的输入/输出是通过并行总线进行的。近期，低功耗，写入/擦除速度快的产品很多，如M
7、icrochip公司的新型8千位、16千位串行EEPROM，最快时钟10MHZ，写入时间5ms，电流3mA,内置写保护功能，可保存数据达200年，承受100万次擦写。Atmel公司的AT24C系列,2023/9/11,chapter 9,5.Using ROM for“random”combinational logic functions,Store the output value of a given truth table in the ROM,the function inputs are connected to the address input.Exp1:the dual po
8、larity decoder.(P.801),84 ROM,POL,I1,I0,Y0,Y1,Y2,Y3,2023/9/11,chapter 9,Exp2:44 multiplier,2023/9/11,chapter 9,More Exp.:ROM在同步时序电路设计中的应用,位序列信号的产生：计数器 ROM法设计一个码长为8位的序列信号发生器，信号序列为01111110。,ADD2,ADD1,ADD0,SEQ,VCC,CLK,D0,D1,D2,D3,84ROM,2023/9/11,chapter 9,2023/9/11,chapter 9,ROM在组合电路设计中的应用,试用84ROM实现如下组
9、合逻辑函数 F1=AB+AC,F2=AB+BC解：先化作标准和式 以输入变量作为ROM的地址，将输出值放入ROM单元。用16字4位ROM实现2输入变量的与非、或非、异或和同或 实现4位二进制码格雷码的转换,2023/9/11,chapter 9,Random-access memory(RAM),both are volatile,Random access means:locations in the memory can be written to or read from in any order,regardless of the memory location that was la
10、st accessed.,store a bit of data in the state of a flip-flop,store a bit of data as a charge in a capacitor,2023/9/11,chapter 9,9.3 Static Random-Access Memory,2nb RAM structure,Address inputs,Data inputs,Control inputs,Data outputs,2023/9/11,chapter 9,SRAM internal structure,Address decoder,A0,A1,A
11、n-1,Storage array(Mb),D0,Db-1,Output circuit,0,1,M,D0,Db-1,WR/RDcontrol,WE_L,CS_L,OE_L,2023/9/11,chapter 9,A static-RAM cellSEL_L、WR_L both negated,D latch hold the data；SEL_L is asserted,tri-state buffer enable,data output(read);SEL_L、WR_L both be asserted,D latch open,a new bit is stored.,store a
12、bit of data in the state of a flip-flop,2023/9/11,chapter 9,synchronous SRAM,A bit of storage is also a latch.Control,addresses and writing or reading data are all occurred at the edge of the same clock.,2023/9/11,chapter 9,9.4 dynamic RAM,Write:Charge the capacitor-store 1;Discharge the capacitor-s
13、tore 0.,Read:Precharge bit line to a voltage halfway between H and L;Set word line to H;The capacitor voltage is H-bit line is pulled slightly higherThe capacitor voltage is L-bit line is pulled slightly lower,store a bit of data in a separate capacitor through a MOS transistor,and need to be refres
14、hed periodically.,2023/9/11,chapter 9,2023/9/11,chapter 9,SDRAM,Control and data operations are referenced to a common clock signal.是single data rate,与系统总线速度同步，在一个时钟周期的上升沿传输一次数据。曾经是PC电脑上最为广泛应用的一种内存类型，分为PC66、PC100、PC133等不同规格，而规格后面的数字就代表着该内存最大所能正常工作系统总线速度,2023/9/11,chapter 9,双数据传输模式同步动态随机存储器，即DDR SDRA
15、M(Double Data Rate Synchronous Dynamic Random Access Memory)是一种继SDRAM后产生的内存技术，为具有双倍数据传输率之SDRAM，其数据传输速度为系统频率之两倍，由于速度增加，其传输效能优于传统的SDRAM。一个时钟周期内传输两次次数据，它能够在时钟的上升期和下降期各传输一次数据。,2023/9/11,chapter 9,存储容量的扩展,1.位扩展 例：从10244bit扩展为10248bit 解：将4比特的芯片增加一片，地址线接至两片芯片的相同的地址端。,2114芯片位扩展,2023/9/11,chapter 9,2.字扩展 例：从10244bit扩展为40964bit,2114芯片字扩展,2-4译码器,D0,A10,A11,A9 A0,A11 A10=10,A11 A10=11,A11 A10=01,A11 A10=00,D3 D0,
