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1、Chapter 2:Computer-System Structures,Computer System OperationI/O StructureStorage Structure Storage Hierarchy Hardware Protection General System Architecture,Uniprocessor Computer-System Architecture,controller,Controller,A device controller is a part of a puter system that makes sense of the signa
2、ls going to,and ing from the CPU processor.Each device controller is in charge of a particular device type.Device controllers use binary and digital codes.Each device controller has a local buffer and a mand register.I/O is from the device to local buffer of controller.I/O devices and the CPU can ex
3、ecute concurrently.Device controllers municate with the CPU by causing an interrupt.,Functions of device controllers,Receiving and understanding the mands of CPUimplementing the data exchange between CPU and devices(format conversion)Recording the status of device to be queried by CPU(status registe
4、r)Identifying the address of each device,Common Functions of Interrupts,Interrupts transfers control to the interrupt service routine generally,through the interrupt vector,which contains the addresses of all the service routines.通常中断通过中断向量把控制传给中断服务程序Interrupt architecture must save the address of t
5、he interrupted instruction.Ining interrupts are disabled while another interrupt is being processed to prevent a lost interrupt.A trap is a software-generated interrupt caused either by an error or a user request.An operating system is interrupt driven.,Interrupt Handling,The operating system preser
6、ves the state of the CPU by storing registers and the program counter.Determines which type of interrupt has occurred:polling vectored interrupt system Separate segments of code determine what action should be taken for each type of interrupt,Interrupt Time Line For a Single Process Doing Output(P21
7、),Chapter 2:Computer-System Structures,Computer System OperationI/O StructureStorage Structure Storage Hierarchy Hardware Protection General System Architecture,I/O Structure,1.No channel(IOP):polling,CPU-Oriented,I/O Structure,2.channel(IOP):,Memory-Oriented,How to output the data in RAM?,Construct
8、 a channel programSubmit the channel program to the corresponding IOP via RAMThe IOP executes the channel programThe IOP notifies CPU by causing an interrupt upon pletion,A channel program is a sequence of I/O instructions executed by the input/output channel processor(IOP).The channel program consi
9、sts of one or more channel mand words.,Two I/O Methods,Synchronous,Asynchronous,Synchronous I/O,After I/O starts,control returns to user program only upon I/O pletion.wait instruction idles the CPU until the next interruptwait loop(contention for memory access).At most one I/O request is outstanding
10、 at a time,no simultaneous I/O processing.,Asynchronous I/O,After I/O starts,control returns to user program,without waiting for I/O pletion.System call request to the operating system to allow user to wait for I/O pletion.Device-status table contains entry for each I/O device indicating its type,ad
11、dress,and state.Operating system indexes into I/O device table to determine device status and to modify table entry to include interrupt.The main advantage of asynchronous I/O is increased system efficiency.,Device-Status Table,I/O Structure,Programmed input/output(PIO)is a method of transferring da
12、ta between the CPU and a peripheral.In general,programmed I/O happens when software running on the CPU uses instructions that access I/O address space to perform data transfers to or from an I/O device.With Direct Memory Access(DMA),the CPU would initiate the transfer,do other operations while the t
13、ransfer is in progress,and receive an interrupt from the DMA controller once the operation has been done.,Direct Memory Access(DMA)Structure,Used for high-speed I/O devices able to transmit information at close to memory speeds.Device controller transfers blocks of data from buffer storage directly
14、to main memory without CPU intervention.Only one interrupt is generated per block,rather than the one interrupt per byte.,Chapter 2:Computer-System Structures,Computer System OperationI/O StructureStorage Structure Storage Hierarchy Hardware Protection General System Architecture,Storage Structure,M
15、ain memory only large storage media that the CPU can access directly.Secondary storage extension of main memory that provides large nonvolatile storage capacity.Magnetic disks rigid metal or glass platters covered with magnetic recording materialDisk surface is logically divided into tracks,which ar
16、e subdivided into sectors.The disk controller determines the logical interaction between the device and the puter.,Moving-Head Disk Mechanism,Positioning time(random-access time)seek time rotational latencytransfer timeTo decrease mechanical delays,i.e.,the seek time and the rotational latency,Disk
17、Scheduling Algorithm,Chapter 2:Computer-System Structures,Computer System OperationI/O StructureStorage Structure Storage Hierarchy Hardware Protection General System Architecture,Storage Hierarchy,Storage systems organized in hierarchy.Speed cost volatility Caching copying information into faster s
18、torage system;main memory can be viewed as a fast cache for secondary storage.,Storage-Device Hierarchy,寄存器缓存主存储器电子盘磁盘光盘磁带,Chapter 2:Computer-System Structures,Computer System OperationI/O StructureStorage Structure Storage Hierarchy Hardware Protection General System Architecture,Hardware Protectio
19、n,Dual-Mode OperationI/O ProtectionMemory ProtectionCPU Protection,Dual-Mode Operation,Sharing system resources requires operating system to ensure that an incorrect program cannot cause other programs to execute incorrectly.Provide hardware support to differentiate between at least two modes of ope
20、rations.至少在两个运行模式之间提供硬件支持1.User mode execution done on behalf of a user.2.Monitor mode(also supervisor mode or system mode)execution done on behalf of operating system.,user,When an interrupt or fault occurs hardware switches to monitor mode.,Dual-Mode Operation(Cont.),Mode bit added to puter hardwa
21、re(PSW)to indicate the current mode:monitor(0)or user(1).,Privileged instructions can be issued only in monitor mode.特权指令只能在管态下执行,monitor,Interrupt/fault,set user mode,I/O Protection,Privileged instructionsAll I/O instructions are privileged instructions.Enable/disable interruptsModify address regis
22、tersSet PSWMust ensure that a user program could never gain control of the puter in monitor mode.,Memory Protection,Must provide memory protection at least for the interrupt vector and the interrupt service routines.In order to have memory protection,add two registers that determine the range of leg
23、al addresses a program may access:base register holds the smallest legal physical memory address.limit register contains the size of the rangeMemory outside the defined range is protected.,A Base And A limit Register Define A Logical Address Space,Hardware Protection,When executing in monitor mode,t
24、he operating system has unrestricted access to both monitor and users memory.The load instructions for the base and limit registers are privileged instructions.,CPU Protection,Timer interrupts puter after specified period to ensure operating system maintains control.Timer is decremented every clock
25、tick.When timer reaches the value 0,an interrupt occurs.Timer monly used to implement time sharing.Timer also used to pute the current time.Load-timer is a privileged instruction.,Chapter 2:Computer-System Structures,Computer System OperationI/O StructureStorage Structure Storage Hierarchy Hardware
26、Protection General System Architecture,General-System Architecture,Given the I/O instructions are privileged,how does the user program perform I/O?System call the method used by a process to request action by the operating system.Usually takes the form of a trap to a specific location in the interru
27、pt vector.Control passes through the interrupt vector to a service routine in the OS,and the mode bit is set to monitor mode.The monitor verifies that the parameters are correct and legal,executes the request,and returns control to the instruction following the system call.,Use of A System Call to Perform I/O,Homework,P41-P42 2.22.32.52.9,
