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1、2023/10/22,Jian Fang,1,集成电路工艺和版图设计概述Jian FangIC Design Center,UESTC,2023/10/22,Jian Fang,2,微电子制造工艺,2023/10/22,Jian Fang,3,IC常用术语,园片：硅片芯片(Chip,Die)：6、8：硅（园）片直径：1 25.4mm6150mm;8200mm;12300mm;亚微米1m的设计规范深亚微米=0.5 m的设计规范0.5 m、0.35 m 设计规范（最小特征尺寸）布线层数：金属（掺杂多晶硅）连线的层数。集成度：每个芯片上集成的晶体管数,2023/10/22,Jian Fang,4,I
2、C工艺常用术语,净化级别：Class 1,Class 10,Class 10,000每立方米空气中含灰尘的个数去离子水氧化扩散注入光刻.,2023/10/22,Jian Fang,5,生产工厂简介,PSI,2023/10/22,Jian Fang,6,Fab Two was completed January 2,1996 and is a State of the Art facility.This 2,200 square foot facility was constructed using all the latest materials and technologies.In thi
3、s set of cleanrooms we change the air 390 times per hour,if you do the math with ULPA filtration this is a Class One facility.We have had it tested and it does meet Class One parameters(without any people working in it).Since we are not making microprocessors here and we dont want to wear space suit
4、s,we run it as a class 10 fab.Even though it consistently runs well below Class Ten.,2023/10/22,Jian Fang,7,Here in the Fab Two Photolithography area we see one of our 200mm.35 micron I-Line Steppers.this stepper can image and align both 6&8 inch wafers.,2023/10/22,Jian Fang,8,Another view of one of
5、 the Fab Two Photolithography areas.,2023/10/22,Jian Fang,9,Here we see a technician loading 300mm wafers into the SemiTool.The wafers are in a 13 wafer Teflon cassette co-designed by Process Specialties and SemiTool in 1995.Again these are the worlds first 300mm wet process cassettes(that can be sp
6、in rinse dried).,2023/10/22,Jian Fang,10,As we look in this window we see the Worlds First true 300mm production furnace.Our development and design of this tool began in 1992,it was installed in December of 1995 and became fully operational in January of 1996.,2023/10/22,Jian Fang,11,Here we can see
7、 the loading of 300mm wafers onto the Paddle.,2023/10/22,Jian Fang,12,Process Specialties has developed the worlds first production 300mm Nitride system!We began processing 300mm LPCVD Silicon Nitride in May of 1997.,2023/10/22,Jian Fang,13,2,500 additional square feet of State of the Art Class One
8、Cleanroom is currently processing wafers!With increased 300mm&200mm processing capabilities including more PVD Metalization,300mm Wet processing/Cleaning capabilities and full wafer 300mm.35um Photolithography,all in a Class One enviroment.,2023/10/22,Jian Fang,14,Currently our PS300A and PS300B dif
9、fusion tools are capable of running both 200mm&300mm wafers.We can even process the two sizes in the same furnace load without suffering any uniformity problems!(Thermal Oxide Only),2023/10/22,Jian Fang,15,Accuracy in metrology is never an issue at Process Specialties.We use the most advanced roboti
10、c laser ellipsometers and other calibrated tools for precision thin film,resistivity,CD and step height measurement.Including our new Nanometrics 8300 full wafer 300mm thin film measurement and mapping tool.We also use outside laboratories and our excellent working relationships with our Metrology t
11、ool customers,for additional correlation and calibration.,2023/10/22,Jian Fang,16,One of two SEM Labs located in our facility.In this one we are using a field emission tool for everything from looking at photoresist profiles and measuring CDs to double checking metal deposition thicknesses.At the he
12、lm,another one of our process engineers you may have spoken with Mark Hinkle.,2023/10/22,Jian Fang,17,Here we are looking at the Incoming material disposition racks,2023/10/22,Jian Fang,18,Above you are looking at a couple of views of the facilities on the west side of Fab One.Here you can see one o
13、f our 18.5 Meg/Ohm DI water systems and one of four 10,000 CFM air systems feeding this fab(left picture),as well as one of our waste air scrubber units(right picture).Both are inside the building for easier maintenance,longer life and better control.,2023/10/22,Jian Fang,19,集成电路（Integrated Circuit,
14、IC）：半导体IC，膜IC，混合IC半导体IC：指用半导体工艺把电路中的有源器件、无源元件及互联布线等以相互不可分离的状态制作在半导体上，最后封装在一个管壳内，构成一个完整的、具有特定功能的电路。,半导体IC,双极IC,MOSIC,BiCMOS,PMOS IC,CMOS IC,NMOS IC,2023/10/22,Jian Fang,20,MOS IC及工艺,MOSFET Metal Oxide Semiconductor Field Effect Transistor.金属氧化物半导体场效应晶体管,Si,金属,氧化物（绝缘层、SiO2）,半导体,MOS(MIS)结构,2023/10/22,J
15、ian Fang,21,栅氧化层厚度：50埃1000埃（5nm100nm）VT阈值电压电压控制,N沟MOS（NMOS）,P型衬底，受主杂质；栅上加正电压，表面吸引电子，反型，电子通道；漏加正电压，电子从源区经N沟道到达漏区，器件开通。,2023/10/22,Jian Fang,22,N衬底,p+,p+,漏,源,栅,栅氧化层,场氧化层,沟道,P沟MOS（PMOS）,VT,VGS,ID,+,-,VDS 0,N型衬底，施主杂质，电子导电；栅上加负电压，表面吸引空穴，反型，空穴通道；漏加负电压，空穴从源区经P沟道到达漏区，器件开通。,2023/10/22,Jian Fang,23,CMOS,CMOS：
16、Complementary Symmetry Metal Oxide Semiconductor 互补对称金属氧化物半导体特点：低功耗,VSS,VDD,Vo,Vi,CMOS倒相器,PMOS,NMOS,I/O,I/O,VDD,VSS,C,C,CMOS传输门,2023/10/22,Jian Fang,24,N-Si,P+,P+,n+,n+,P-阱,D,D,Vo,VG,VSS,S,S,VDD,CMOS倒相器截面图,CMOS倒相器版图,2023/10/22,Jian Fang,25,A NMOS Example,2023/10/22,Jian Fang,26,pwell,PwellActivePoly
17、N+implantP+implantOmicontactMetal,2023/10/22,Jian Fang,27,Ntype Si,SiO2,光刻胶,MASK Pwell,2023/10/22,Jian Fang,28,Ntype Si,SiO2,光刻胶,光刻胶,MASK Pwell,2023/10/22,Jian Fang,29,Ntype Si,SiO2,光刻胶,光刻胶,SiO2,2023/10/22,Jian Fang,30,Ntype Si,SiO2,SiO2,Pwell,2023/10/22,Jian Fang,31,pwell,PwellActivePolyN+implantP+
18、implantOmicontactMetal,2023/10/22,Jian Fang,32,Ntype Si,SiO2,Pwell,SiO2,光刻胶,MASK active,MASK Active,Si3N4,2023/10/22,Jian Fang,33,Ntype Si,SiO2,Pwell,SiO2,光刻胶,光刻胶,MASK active,MASK Active,Si3N4,2023/10/22,Jian Fang,34,Ntype Si,SiO2,Pwell,SiO2,光刻胶,光刻胶,Si3N4,2023/10/22,Jian Fang,35,Ntype Si,SiO2,Pwell,
19、SiO2,场氧,场氧,场氧,Pwell,Si3N4,2023/10/22,Jian Fang,36,Ntype Si,SiO2,Pwell,场氧,场氧,场氧,Pwell,2023/10/22,Jian Fang,37,Ntype Si,SiO2,Pwell,SiO2,场氧,场氧,场氧,Pwell,poly,2023/10/22,Jian Fang,38,active,pwell,PwellActivePolyN+implantP+implantOmicontactMetal,2023/10/22,Jian Fang,39,Ntype Si,SiO2,Pwell,SiO2,MASK poly,场
20、氧,场氧,场氧,Pwell,poly,光刻胶,2023/10/22,Jian Fang,40,Ntype Si,SiO2,Pwell,SiO2,MASK poly,场氧,场氧,场氧,Pwell,光刻胶,poly,2023/10/22,Jian Fang,41,Ntype Si,SiO2,Pwell,SiO2,场氧,场氧,场氧,Pwell,poly,2023/10/22,Jian Fang,42,Ntype Si,SiO2,Pwell,SiO2,场氧,场氧,场氧,Pwell,poly,2023/10/22,Jian Fang,43,active,pwell,poly,PwellActivePol
21、yN+implantP+implantOmicontactMetal,2023/10/22,Jian Fang,44,Ntype Si,SiO2,Pwell,SiO2,MASK N+,场氧,场氧,场氧,Pwell,poly,光刻胶,2023/10/22,Jian Fang,45,Ntype Si,SiO2,Pwell,SiO2,场氧,场氧,场氧,Pwell,光刻胶,poly,N+implant,2023/10/22,Jian Fang,46,active,pwell,poly,P+implant,PwellActivePolyN+implantP+implantOmicontactMetal,
22、2023/10/22,Jian Fang,47,Ntype Si,SiO2,Pwell,SiO2,MASK N+,场氧,场氧,场氧,Pwell,poly,光刻胶,光,2023/10/22,Jian Fang,48,Ntype Si,SiO2,Pwell,SiO2,场氧,场氧,场氧,Pwell,poly,光刻胶,P+implant,2023/10/22,Jian Fang,49,Ntype Si,SiO2,Pwell,SiO2,场氧,场氧,场氧,Pwell,poly,2023/10/22,Jian Fang,50,active,pwell,poly,P+implant,N+implant,Pwe
23、llActivePolyN+implantP+implantOmicontactMetal,2023/10/22,Jian Fang,51,Ntype Si,SiO2,Pwell,SiO2,MASK Omicontact,场氧,场氧,场氧,Pwell,poly,2023/10/22,Jian Fang,52,active,pwell,poly,N+implant,omicontact,PwellActivePolyN+implantP+implantOmicontactMetal,2023/10/22,Jian Fang,53,Ntype Si,SiO2,Pwell,SiO2,MASK met
24、al,场氧,场氧,场氧,Pwell,poly,metal,metal,metal,2023/10/22,Jian Fang,54,2023/10/22,Jian Fang,55,双极型IC及工艺,N,P,N,基极,集电极,发射极,P,N,P,基极,集电极,发射极,C,B,E,IB,IC,IE,C,B,E,IB,IC,IE,NPN晶体管,PNP晶体管,2023/10/22,Jian Fang,56,VCE,iC,iB,VCE(sat),iR,双极型晶体管输出特性,放大区,饱和区,电流放大能力；电流驱动；,2023/10/22,Jian Fang,57,基极,发射极,2023/10/22,Jian
25、 Fang,58,BiCMOS:双极(Bipolar)与CMOS相容技术。BiCMOS可以将双极器件与CMOS器件制作在同一芯片上，使之具有双极电路的高速度、高驱动能力、高模拟精度，又具有CMOS电路的低功耗、高集成度等特性。BiCMOS工艺较之CMOS工艺和双极工艺都复杂，制作周期长，产品成品率比CMOS低，成本比CMOS高。高性能双极工艺与CMOS的VLSI工艺80的工艺是相同的，在CMOS生产线上，只要改动或增添一部分工序，增添一部分设备，就可以制作BiCMOS芯片。,BiCMOS,2023/10/22,Jian Fang,59,版图设计（layout）及相关技术,2023/10/22,
26、Jian Fang,60,Cell development(Analog/digital)Analog design,Schematic entry(transistor symbols)Analog simulation(SPICE models)Layout(layer definitions)Design Rule Checking,DRC(design rules)Extraction(extraction rules and parameters)Electrical Rule Checking,ERC(ERC rules)Layout Versus Schematic,LVS(LV
27、S rules),2023/10/22,Jian Fang,61,LayoutDrawing geometrical shapes:Defines layout hierarchy Defines layer masksRequires detailed knowledge about CMOS technologyRequires detailed knowledge about design rules(hundreds of rules)Requires detailed knowledge about circuit designSlow and tediousOptimum perf
28、ormance can be obtained,2023/10/22,Jian Fang,62,图形层的定义,N+implant,metal,pwell,active,Poly,定义若干图层,每层对应一张掩膜版,pwell,active,poly,N+implant,P+implant,omicontact,metal,2023/10/22,Jian Fang,63,Lib A,Lib B,Lib C,Cell 1,Cell 2,Cell 3,Tech,inst 1,inst 2,Inst 3,版图库的组织,一个库对应一个特定的工艺 针对该工艺的设计规则,和环境设定放在Tech文件中.一个库可
29、以包含若干不同层次的Cell.,2023/10/22,Jian Fang,64,版图数据交换文件,GDSII格式 CIF格式 EDIF格式,基本图形,基本操作,2023/10/22,Jian Fang,65,DRC Design Rule Check Checks geometrical shapes:width,length,spacing,overlap,etc.,1.单层规则该规则包括各层的最小宽度a及同层间距b,2023/10/22,Jian Fang,66,CMOS电路规则,2.层间规则（包括各层间的间距、包围、迭搭的大小）,2023/10/22,Jian Fang,67,说明 标号
30、 尺寸（um）有源区包围欧姆孔 a 4 金属（铝）包围欧姆孔 b 3 多晶硅包围欧姆孔 c 4 n+、p+注入区包围有源区 d 5 n+、p+保护环有源区 e 10 n+、p+保护环宽度 f 5 nmos、pmos多晶硅栅宽度 g 6 多晶硅栅伸出有源区 h 12 多晶硅栅与n+、p+保护环迭搭 i 2 多晶硅栅铝布线 j 1 p阱包围p+保护环 k 2.,2023/10/22,Jian Fang,68,DRC文件例子(片断),(drc metal(width 1.00)(drc metal(sep 0.80),(drc metal omicont(enc 0.30)(drc poly omi
31、cont(enc 0.40),2023/10/22,Jian Fang,69,EXTRACT,用图层间的相对关系判定器件及相互连接关系.例如:Poly跨过Active,即同时出现Poly和Active表明有一个MOS器件.,Extracts electrical circuit:transistors,connections,capacitance,resistance,2023/10/22,Jian Fang,70,EXTRACT文件例子(片断),(extractDevice ngate(poly G)(nsd S D)(pwell1 B)nmos4 symbol analogLib)(ex
32、tractDevice pgate(poly G)(psd S D)(sub B)pmos4 symbol analogLib)pgateWidth=measureParameter(length(pgate coincident poly)0.5)pgateLength=measureParameter(length(pgate inside poly)0.5)saveParameter(pgateWidth W)saveParameter(pgateLength L)ngateWidth=measureParameter(length(ngate coincident poly)0.5)n
33、gateLength=measureParameter(length(ngate inside poly)0.5)saveParameter(ngateWidth W)saveParameter(ngateLength L),2023/10/22,Jian Fang,71,LVS,Layout versus schematic transistors:parallel or serial Compares electrical circuits:(schematic and extracted layout),2023/10/22,Jian Fang,72,ERC Electrical rul
34、e check Checks electrical circuit:unconnected inputsshorted outputscorrect power and ground connection,2023/10/22,Jian Fang,73,Digital design,Behavioral simulation.Simulation/timing verification with estimated back-annotationPlace and route(place and route rules)Design Rule Check,DRC(DRC rules)Loadi
35、ng extraction(rules and parameters)Simulation/timing verification with real back-annotationDesign export.,2023/10/22,Jian Fang,74,Place and Route,Generates final chip from gate level netlistGoals:Minimum chip sizeMaximum chip speed.Placement:Placing all gates to minimize distance between connected g
36、atesFloor planning tool using design hierarchySpecialized algorithms(min cut,simulated annealing,etc.)Timing drivenManual interventionVery compute intensive,Hierarchy based floor planning,2023/10/22,Jian Fang,75,Routing:Channel based:Routing only in channels between gates(few metal layers:2)Channel
37、less:Routing over gates(many metal layers:3-6)Often split in two steps:Global route:Find a coarse route depending on local routing densityDetailed route:Generate routing layout,Channel based,Channel less,2023/10/22,Jian Fang,76,Performance of sub-micron CMOS ICs are to a large extent determined by p
38、lace&route.Loading delays bigger than intrinsic gate delaysWire R-C delays becomes important in sub-micronClock distribution over complete chip gets critical at operating frequencies above 100Mhz.,Delay,Technology,1.0u,0.5u,0.25u,0.1u,25ps,50ps,100ps,200ps,Gate delay,Wire load delay,2023/10/22,Jian
39、Fang,77,2023/10/22,Jian Fang,78,2023/10/22,Jian Fang,79,2023/10/22,Jian Fang,80,集成电路设计（物理层）,2023/10/22,Jian Fang,81,2023/10/22,Jian Fang,82,2023/10/22,Jian Fang,83,2023/10/22,Jian Fang,84,2023/10/22,Jian Fang,85,2023/10/22,Jian Fang,86,2023/10/22,Jian Fang,87,2023/10/22,Jian Fang,88,参考文献:清华大学出版社 朱正涌 清华大学出版社 杨之廉,2023/10/22,Jian Fang,89,OVER,
