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1、Cadences Solution for High-Speed Design,Agenda,What is High-Speed Design?Ideal High-Speed Design ProcessIntroduction to SPECCTRAQuest Power IntegritySPECCTRAQuest Demonstration,The Day of“High-Speed”Has Come,“Pc-board designers,meanwhile,were retooling in 1999 for high-speed design.Signal integrity,
2、once confined to high-end boards,has become everybodys problem”Richard Goering,commenting on why the PCB layout market grew 20%while the IC layout market shrunk 30%,in EETimes 4/10/2000 page 70,Welcome Networking!,HammerheadNetworks,Agenda,What is High-Speed Design?Ideal High-Speed Design ProcessSPE
3、CCTRAQuest DemonstrationIntroduction to SPECCTRAQuest Power Integrity,NOW,What is“High-Speed”?,Over 50 MHzis“High-Speed”,“High-Speed”isnt relatedto frequency,its a functionof rise times,A net is“High-Speed”when itsround-trip delay is greaterthan twice its edge-speed,A signal is“High-Speed”when it is
4、 faster thananything youve designed before,“High-Speed”occurs whenskin effect and dielectricloss effects become important,Huh?,Question:Which is a“High-Speed”Problem?,Answer:They BOTH Are!,Definition of High-Speed,A net can be considered High-Speed when you have to do something other than simply con
5、nect it.,High-Speed Design Involves 2 Things,Nets that are understood,and must be constrained Nets that must be analyzed to be understood,and then constrained,Nets that are understood,and must be constrained Nets that must be analyzed to be understood,and then constrained,SDRAM DIMM Layout,MODELS,Da
6、tasheets,Front-side Bus Simulation,Most Tools Force You to Choose,GreatSimulator!,Analyze,Constrain,GreatLayoutSystem!,Hmm.,But for High-Speed You Need BOTH,All in ONE integrated&interactive environment!,Lets Go!,SPECCTRAQuest:Integrated Constraint&Analysis,Model Development&Verification,Topology En
7、try&Floorplanning,Constraint Driven Layout,Analyze,Constrain,SPECCTRAQuest helps you manage the process of High-Speed PCB development through both Simulation Analysis&Constraint-Driven Layout tasksA Complete Solution!,Pre-Route Soln-Space Analysis,Expanding Existing Process,PhysicalModelCreation,Out
8、line/Floorplan/Room Def/,SchematicModelCreation,SchematicCreation,SCHEMATIC,LAYOUT,To Final Verification,netlist,SI CleanRoute,Back-Annotate,PCBRouting,Agenda,What is High-Speed Design?Ideal High-Speed Design ProcessSPECCTRAQuest DemonstrationIntroduction to SPECCTRAQuest Power Integrity,NOW,Ideal H
9、igh-Speed Design Flow,Model Development&Verification,Topology Entry&Floorplanning,Constraint Driven Layout,Analyze,Constrain,Development Process Flow,Pre-Route Soln-Space Analysis,Model Development&Verification,Need Flexible Device Modeling Language(DML),Todays models come in many styles and formats
10、Cadence DML can model all formats AND advanced behaviors(for example,Merced/Itanium),QuadModels,Package,Transmission Line,Connector,CableModels,EBDModels,CadenceDML,cant do“M”element today,Ideal High-Speed Design Flow,Model Development&Verification,Topology Entry&Floorplanning,Constraint Driven Layo
11、ut,Analyze,Constrain,Development Process Flow,Pre-Route Soln-Space Analysis,Pre-Route Soln-Space Analysis,Pre-Route Solution Space Analysis,Exhaustive“pre-layout”analysis of manufacturing and design variancesUsed to define topologies,routing rules and termination strategiesCrosstalk and data pattern
12、 dependencies may be taken into considerationSwept-parameter analysis is used extensively to cover all combinations of conditionsNeed flexibility to define any kind of simulation and any kind of measurement criteria,Output of pre-layout process is an electronic constraint file that can be used to gu
13、ide the layout process,Analyze,Topology Templates,Derive and Save“Solution Space”,Constrain,Ideal High-Speed Design Flow,Model Development&Verification,Topology Entry&Floorplanning,Constraint Driven Layout,Analyze,Constrain,Development Process Flow,Pre-Route Soln-Space Analysis,Topology Entry&Floorp
14、lanning,High-Speed PCB Design Now Requires Both Electronic Inputs to Floorplanning&Routing,Topology Entry and Floorplanning,Design rules derived from solution space analysis guide the placement processConstraint Manager spreadsheets plays a key role in guiding/evaluating component placementMargin co
15、lumns show difference between constraint and design valueFast feedbackColor-coded status,Topology Templates,Ideal High-Speed Design Flow,Model Development&Verification,Topology Entry&Floorplanning,Constraint Driven Layout,Analyze,Constrain,Development Process Flow,Pre-Route Soln-Space Analysis,Const
16、raint Driven Layout,ConceptHDLCapture,SPECCTRAQuestExploration,SPECCTRAQuestFloorplanning,Allegro/APDLayout,Constraint Manager,Capture,Exploration,Floorplanning,Layout,GUI,GUI,GUI,GUI,Constraints,Constraints,Constraints,Constraints,?,?,?,ePlanner/QUAD,SPICE,HyperLynx,ViewDraw,ICX,Design,Board Statio
17、n,PADS,VeriBest,Architect,ePlanner,Constraint Management Today,PSD 14.0 Constraint Manager,Common,powerful environment for constraint entry/editing/management and verificationSingle mechanism for managing constraints throughout the design process,Constraint Manager Key Features,Spreadsheet-based gra
18、phical interfaceNo cryptic formats or cumbersome updatingProvides unsurpassed Integration across the entire design flowConsistent Front to Back solutionNo messy translations with static constraint data Directly integrated with schematic and PCB databasesAnalysis engines can update spreadsheet data i
19、nteractively,Constraint Manager Hierarchy,Allows constraints to be managed hierarchicallyGroups of rules are maintained as Electrical Constraint Sets(ECSets)Provides single point for updating rules or assigning to netsECSets can be applied to groups of nets(buses)with individual overrides,Constraint
20、 Manager Systems,Support for system level constraintsConstraints can span PCB boundaries,Topology Templates,Constraint Driven Layout,Guides:FloorplanningHand LayoutAuto-Route,Constraint Driven Layout,Design rule violations during interactive routing are identified in real-timeAutorouter follows desi
21、gn rules-powerful integration with SPECCTRA!Because solution space analysis has defined a set of conditions under which the nets are known to work,chance of first-pass success is high.Nets can be ripped up and rerouted,as long as they still adhere to the design rules,Ideal High-Speed Design Flow,Mod
22、el Development&Verification,Topology Entry&Floorplanning,Constraint Driven Layout,Analyze,Constrain,Development Process Flow,Pre-Route Soln-Space Analysis,Post Route Analysis Verification,Verification,Agenda,What is High-Speed Design?Ideal High-Speed Design ProcessIntroduction to SPECCTRAQuest Power
23、 IntegritySPECCTRAQuest Demonstration,NOW,SPECCTRAQuest Power Integrity Module,The Future of Power Delivery System Design,SPECCTRAQuest Power Integrity,Innovative technology developed and proven by Sun Microsystems,now commercialized by Cadence Design Systems,Inc.to address Power Delivery issues in
24、high-speed PCB System Designs.A design tool/methodology used to design and optimize the frequency-dependent characteristics of Power Delivery Systems in high-speed system designsAn integrated solution to allow many quick iterations of“change-simulate-analyze”,Power Delivery Requirements Trend,Power
25、dissipation and longer battery life fueling decreasing chip power supply voltages Maximum allowable supply ripple decreases accordingly SoC,SiP fueling trend towards devices with large number of devices The instantaneous switching current required is enormousThe maximum acceptable power supply rippl
26、e voltage determines the target impedance which must be maintained across the PCBMaximum supply impedance must be less than 0.002 Ohms,Power Delivery System Design Challenges,Power supply droopAlters system timing and can cause Setup failuresCan cause sampling errors that results in a system crashUn
27、reliable power delivery system design can cause increased common-mode EMI preventing product shipment due to compliance problems Power delivery system impedance is frequency-dependentMust be controlled for all frequency range of all transient currents,Increases Development Costs and Time to Market i
28、s LOST!,Power Delivery System Design-How it is done today,Standalone analysis toolsDesign data translation is left up to the userChanges to the design resulting from simulation is manualUse Time Domain simulationPower delivery system impedance is frequency-dependent!With only time domain simulation,
29、it is like searching for needle in a haystackOver design-add more de-coupling capacitors than necessaryExpensive solution that may not work,The Cadence approach,Allow users to determine the needs of the power delivery systemTarget impedanceDecoupling capacitor requirements Provide frequency domain a
30、nalysis to find problem areasProvide an integrated PCB design editor to optimize capacitor placement,Develop reliable power delivery systemwhile shortening design cycle time,SPECCTRAQuest Power Integrity-Software Components,Frequency-domain analysis engineIntegrated PCB editor that includes Decoupli
31、ng capacitor placement environment Impedance requirements calculatorDecoupling requirements wizardHigh speed capacitor library/library editor,Isolating Decoupling Problem Areas,Device Placement Decoupling Capacitors,Capacitors can be selected from the decoupling“menu”and placed into the designThe ef
32、fective decoupling radius is automatically displayed as the capacitor is positionedDesigners continue to adjust capacitor selection&placement until performance of the PDS is acceptable,Allows many“change-simulate-analyze”cycles in a short time,Release,Available with PSD release version 14.1Scheduled
33、 for late Q2,2001First release available on Sun Solaris(7/8)onlyOther platforms to follow with next major release,SPECCTRAQuest Power Integrity-Summary,Innovative technology developed and proven by Sun Microsystems,commercialized by CadenceCombined toolset and methodology for the design and analysis
34、 of high performance power delivery systemsOffered as an option to SPECCTRAQuest,integrated with AllegroPart of Cadences complete family of Signal Integrity/Power Delivery/EMI solutions,Shortens Development Cycle and Time to Market!,Agenda,What is High-Speed Design?Ideal High-Speed Design ProcessInt
35、roduction to SPECCTRAQuest Power IntegritySPECCTRAQuest Demonstration,NOW,SPECCTRAQuest Demonstration,(please ask questions as we proceed!),What You Will See,Intel PIII/BX Reference Design100 MHz Front-Side BusAnalysis&Constraint ProcessBoard LevelElectrical LevelConstraint IntegrationAdvanced Proce
36、ssing,Post-Route DRC Verification,DRC checks identify areas which do not comply with design rulesNet is marked visuallyIdentifies which constraint was violatedDRC provides a“first pass”check faster than simulationDesign rules can also be applied without ripping up etch,to pinpoint problems in boards
37、 routed before design rules were available,Post-Route Analysis Verification,Post-layout simulation now becomes a“verification”processChances of first-time success are high if a thorough solution-space analysis was performedNets can be extracted individually and analyzed in-depth if problems are foun
38、dSQ has the only optimized spice analysis engine that is integrated with PCB layout and field solvers,SPECCTRAQuest:Integrated Constraint&Analysis,Model Development&Verification,Topology Entry&Floorplanning,Constraint Driven Layout,Analyze,Constrain,Development Process Flow,Pre-Route Soln-Space Analysis,
