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1、,Verilog,Matt Tsai,Verilog ApplicationIntroduction to Cadence SimulatorsSample DesignLexical Conventions in VerilogVerilog Data Type and Logic SystemStructural ModelingModeling DelayUsing Compiler ControlsVerilog OperatorsBehavioral ModelingSupport for VerificationIntroduction to Using a Verilog Tes
2、t BenchModeling MemoriesHigh Level Constructs in VerilogUser Defined PrimitivesAnnotating SDF Timing,IEEE 1364-1995,IEEE 1364-2001Behavioral:無法看出電路特性RTL:可以看出電路特性(logic synthesis)Structural:bulit-in primitives,UDPsRTL and structural 可混合描述Behavioral 和 RTL的區分要靠經驗,Behavioral for(;)for(;).,RTLalways(sl o
3、r a or b)if(!sl)out=a;else out=b;,Compilation(1)Initialization(2)Simulation(3)Verilog-XL simulator:Interpretive不會有暫存檔(1)(2)(3)一次完成NC Verilog simulator:compiled simulationncviog(1)ncelab(2)ncsim(3)當project很大時,只針對要修改部分重新compile即可VHDL and Verilog可以作整合Simulation algorithmsTime-based(SPICE)Event-based(Ve
4、rilog-XL and NC Verilog)Cycle-based(依照clock,更大的time-based),3-9,3-3,verilog mux.v testbench.vverilog f run.fThe waveform display tool-signalscanRead data from database SHM database(非IEEE standard,only Cadence)VCD(Value Change Dump)database(IEEE standard),initial begin$shm_open(“lab.shm”);$shm_probe(“
5、AS”);end,initial begin$dumpfile(“lab.dump”);$dumpvars();end,3-17,4-26,3-27,Testbench-behavioralProcedural blockInitialalways,Templatemodule testbench/Data type declaration/Instantiate modules/Apply stimulus/Display resultsendmodule,module testbench/Data type declaration reg a,b,sel;wire out;/Instant
6、iate modules MUX2_1 mux(out,a,b,sel);/Apply stimulus initial begin a=0;b=0;sel=0;#5 b=0;#5 b=1;sel=1;#5a=1;$finish;end/Display results initial$monitor($time,”out=%b a=%b sel=%b”,out,a,b,sel);endmodule,4-15,Waveform database(SHM and VCD),$shm_open(“lab.shm”);$shm_probe();$shm_close;$shm_save;,$dumpfi
7、le(lab.dump”);$dumpvars();$dumpflush;$dumpoff;$dumppon;$dumplinit();$dumpall;,include global.vverilog mux.v global.vtimescale 1ns/100 psLumped delaynor n1(net1,a,b);or#3 o1(out,c,net1);Distributed delaynor#2 n1(net1,a,b);or#1 o1(out,c,net1);Module path delaySpecify(A=O)=2;(A=O)=3;(A=O)=1;/state depe
8、ndent path delay if(a)(b=x)=(5:6:7);/state dependent delay 無else的語法Endspecify specify block,Inside codeCommand line,8-3,8-16,Selecting simulation delay mode,Command line+delay_mode_unit+delay_mode_zero+delay_mode_path+delay_mode_distributed,Inside codedelay_mode_unitdelay_mode_zerodelay_mode_pathdel
9、ay_mode_distributed,Unit and zero delay modes:ignores all specify blocks,and reduces gate to unit or zero value.Distributed mode:ignores specify blocks,but leaves gate delays alonePath mode:ignores gate delays,but leaves specify blocks alone,Parallel connection(a,b=q,qb)=15;(a=q)=15;(b=qb)=15;Full c
10、onnection(a,b*q,qb)=15;(a=q)=15;(b=q)=15;(a=qb)=15;(b=qb)=15;,Timing checks in Verilog(物理特性)Setup,hold,pulse width,clock period,skew,recoverySDF(Standard Delay Format)tool-independent text format for representing timing dataAllows timing data to be shared between toolsInterconnect delay因製程技,使interco
11、nnection delay比gate delay大,下晶片需SDF FileIOPATH delayA delay on legal path from an input port to an output port of a device,8-38,21-5,8-30,Using Compiler Controls,Vendor-supplied verilog librariesSimulating with verilog librariesEncrypting your verilog source codeAdditional simulator-specific topics,M
12、odeling component libraries,To create verilog model librariesModel each component(or cell)as separate modulePlace related modules in either one file or one directoryYou can model the functionality of each cell at two levelsStructuralUDPs,combinational logic and simple sequential logicBehavioralProce
13、dural blockRAM,ROM,9-5,verilog test.v v lib.v若無-v會全部compile有-v用到才compile也可無celldefine及-v,如一般的file,verilog test.v y./mylib+libext+and2.v檔案名稱要和module名字相同一個file內只能有一個module這些files全部都要放在library directory,(Verilog model library directory),The uselib compiler directive(only Cadence),module adder(c_out,sum
14、,a,b,c_in);Output c_out,sum;Input a,b,c_in;uselib dir=/libs/FAST_LIB/SN7486 u1(half_sum,a,b);Uselib dir=/libs/TTL/libext=.v file=/libs/TTL/udp.libSN7408 u2(half_c,a,b);SN7486 u2(sumc,c_in,half_sum);SN7432 u2(c_out,tmp,half_c);SN7486 u1(half_sum,a,b);/ERRORendmodule,9-18,Sizing and signing in Verilog
15、,等號右邊一定是對的,指定到左邊時會自動truncate,module sign_size;reg 3:0 a,b;reg 15:0 c;reg 3:0 regb,rega,num;initial begin a=-1;/1111 b=8;c=8;#10 b=b+a;/10111-0111endinitial#30 num=regb%rega;/num的正負號和regb相同endmodule,10-5,Equality operator=:assignment operator=:the equality operator(數值比對)1=1=:the identity operator(型態上
16、)x=xval=rega=regb;/rega=1,regb=1,val=1val=rega=regc;/rega=1,regb=x,val=xval=rega=regc;/rega=z,regb=z,val=xval=rega=regb;/rega=x,regb=x,val=1Conditional operator assign out=sel=2b00?a:sel=2b01?b:sel=2b10?c:d;,10-21,10-28,Concatenationnew=regc4:3,regd7:5,regb2;Replicationnew=4regb,2regc;Procedural blo
17、ckBehavioral modeling,not structural modelingTwo type:initial,alwaysIt has the following componentProcedural assignment statementsHigh-level constructs(loops,conditional statements)Timing controlsProcedural assignmentInside procedural blocks等號左邊要reg才行,Procedural timing control#,wait所有的procedural blo
18、cks同時執行,always wait(set)begin(posedge clk)#3 q=1;#10 q=0;wait(!set);end,1.有可能會有race condition,但並非每次都會有race condition2.race condition 是simulation 才會有,可以改變set信號再去 Simulation就可以了3.實際電路不會,因本身就有delay了,11-39,Inter-assignmenttemp=b;(posedge clk)a=temp;Intra-assignmenta=(posedge clk)b;,posedge clk右邊算出左右,右邊算
19、出,暫存在bposedge clk左右,Data,c,b,clk,IntercIntrab,Conditional statementsif-elsecaseIf-else階層超過2層時會有判斷優先權順序的路出現,故改用case若無else敘述,電路會變得很大Continuous assignment(assign)Procedural block中不可用assignwire out;assign out=a/implicit,Verification system functions and tasks$time(64-bits)$stime(32-bits)$realtime(real n
20、umber)$display$strobe$write$monitorPrinting formatted time information$timeformat(,)$timeformat(-9,2,”ns,10);$display(“%t”,$realtime);,To read the current simulation time,To support text output,$write vs.$display:$display會自動換行$strobe一定在event-query的最後面,initial begin#10 date=20;$strobe($time,data);/30
21、$display($time,data);/20data=30;end,initial begin integer MCD1;/每個檔只有一個bit為1,有一個bit保留,故最多可以開31個檔 MCD1=$fopen(“lab.dat”);$fdisplay(MCD1,”system reset at time%d”,$time);$fwrite(MCD1,”system reset at time%d”,$time);$fstrobe(MCD1,”system reset at time%d”,$time);$fmonitor(MCD1,”system reset at time%d”,$t
22、ime);$fclose(MCD1)end,File output,14-20,File input$readmemb$readmemh,reg 0:7 mema0:1023;readmemb(“mem_file.txt,mema);,0000_00000110_0001 0011_0010/addresses 3-255 are not defined100/hex1111_11003FF1110_0010,mem_file.txt,0000000001100001001100101111110011100010,0,256,1023,14-26,Design organization,In
23、clude files,Design files,File input:Simulus,Expect patterns,Vendor libraries,File output:Stimulus,resultpatterns,simulator,simulation,compilation,Include files,module clk_gen(clk);output clk;reg clk;include“common.txt”.endmodule,/common.txtparameter initial_clock=1;parameter period=1;parameter max_c
24、yc=1;parameter sim_end=period*max_cyc;,1.parameter獨立在某一檔案中,並且詳細說明2.改變parameter,重新compile即是新的design,Testbench給pattern的方式,In lineLoop(behavioral),pattern要有規則array,/in lineinitialfork data_bus=8h00;addr=8h3f;#10 data_bus=8h45;#30 addr=8h45;#60$finish;join,/loopinitialbegin for(;)(negedge clk)stimulus=1
25、;#20$finish;end,/arrayinitialbegin#20 stimulus=stim_array0;#20 stimulus=stim_array1;#20 stimulus=stim_array2;end,Verilog task and function,Task:input,output,inout,timingFuinction:input,return value,combinational,可建立自己的operatorFunction 一定在等號右邊,不一定要在procedural blcok中Task:只能出現在procedural block中,always#
26、5 clk=!clk;task ngg_clocks input 31;0 number_of_edges;repeat(number_of_edges)(negedge clk);endtaskinitial begin neg_clocks(3);end,module foo;input 7:0 loo;output 7:0 goo;wire 7:0 goo=test(loo);function 7:0 test input 7;0 bus;test=return_test;endfunctionendmodule,17-7,不可synthesize,=uselibinitialmemor
27、y/WaitString(5-17)Named event(11-17),所有的module不一定有 I/O Port名稱大小寫有差!但compiler會視為相同東西宣告integer:Enter 旁的dot宣告compiler directive:ESC 下的dotX unknown state is used for testNet is unconditional update,Register is conditional updateDefine/Parameter difference(6-25)L&H state(7-11),User Define PrimitiveVerilo
28、g 可以加密!(9-36)語法是+autoprotected 或 protect endprotectZero delay loop(8-11)Register array and memory addressing(6-30),Lab,Cadence:/cadence/bin/icfb verilog signalscanSynopsys:source synopsys.cshrcda&,#dollarsetenv SYNOPSYS/usr/synopsyssetenv LM_LICENSE_FILE 26585lsfcusetenv SYNOPSYS_KEY_FILE$SYNOPSYS/a
29、dmin/license/keyset path=(/usr/bin/X11$SYNOPSYS/sparcOS5/syn/bin$SYNOPSYS/iview2/bin$SYNOPSYS/sos/bin$path)source$SYNOPSYS/admin/install/sim/bin/environ.cshalias da design_analyzer#define COSSAP environment variables for the COSSAP user(csh version)#SYNOPSYS software is installed in/usr/synopsys#set
30、env COSSAP_DIR/usr/synopsys/sparcOS5/cossap#setenv COSSAP_KEYS/usr/synopsys/admin/license/key#network wide writable file holding the netlist number#setenv COSSAP_NEWSIM_SIM/usr/synopsys/sparcOS5/cossap/admin/install/newsim.sim#the default COSSAP project is derived from the login directory#if(!$?COSS
31、AP_PROJECT)setenv COSSAP_PROJECT basename$HOME#define the COSSAP PATH#set path=($COSSAP_DIR/bin/opt/SUNWspro/bin$path)#define a few directory switching commands for COSSAP#alias cdir cd$HOME/cossap/$COSSAP_PROJECT/c#alias ddir cd$HOME/cossap/$COSSAP_PROJECT/d#alias vdir cd$HOME/cossap/$COSSAP_PROJEC
32、T/v#alias tdir cd$HOME/cossap/costmp#define COSSAP project switching command#alias scp set scp_project=!:*;source$COSSAP_DIR/appl/utils/scp.csh#set limit for file descriptors#limit descriptors 256,synopsys.cshrc,designer=Chin-Yi Tsai;company=CICsearch_path=/app/cadtool/library/CIC_CBDK35_V3/Synopsys
33、+search_path;link_library=cb35os142.db dw01.sldb,dw02.sldb,dw03.sldb,dw04.sldb,dw05.sldb;target_library=cb35os142.db;symbol_library=generic.sdb class.sdb;synthetic_library=standard.sldb.dw01.sldb.dw02.sldb.dw03.sldb.dw04.sldb.dw05.sldb;vhdlout_use_packages=IEEE.std_Logic_pass_ponentsvhdlout_write_top_configuration=true,.synopsys_dc.setup(design_analyzer的設定檔)可更改designer及company欄位,其他不可更動,除非設計需要,如外加記憶體模組,synopsys_dc.setup,/home/VLSILAB/ta/CB/home/VLSILAB/ta/CB/da/synopsys.cshrc,
