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1、第二章 部分习题答案,2.1(d)67.248=110111.0101002(e)10100.11012=14.D16(i)101111.01112=57.348(j)15C.3816=101011100.001112,2.2(a)12348=10100111002=29C16(e)7436.118 2=F1E.2416,2.3(b)7E6A162=771528(e)9E36.7A16 2=117066.3648,2.5(e)10100.11012=20.812510(j)15C.3816=348.2187510,2.6(b)348910=66418(f)2385110=5D2B16 补充：1
2、25.1710=1111101.001012,2-5,2.7(a),C 1 1 0 0 1 0 0,1 1 0 0 1 1,1 1 0 1 0,+,1 0 0 1 1 0 1,2.8(b),B 1 1 1 0 0 0 0,1 0 0 1 1 1,1 0 1 0 1 0,+,1 1 1 1 0 1,2.9(b),C 1 1 1 1 0,5 7 7 3 4,1 0 6 6,+,6 1 0 2 2,2.10(c),C 1 0 1 1 0,F 3 5 B,2 7 E 6,+,1 1 B 4 1,2.11,8-bit signed-magnitude,+25,8-bit twos,8-bit ones,
3、00011001,00011001,00011001,+120,01111010,01111010,01111010,+82,01010010,01010010,01010010,-42,10101010,11010110,11010101,-6,10000110,11111010,11111001,-111,11101111,10010001,10010000,2.12(b),C 1 1 1 1 1 1 1 1 0,1 0 1 1 1 1 1 1,1 1 0 1 1 1 1 1,+,1 0 0 1 1 1 1 0,(c),C 1 1 1 0 0 0 1 0,0 1 0 1 1 1 0 1,0
4、 0 1 1 0 0 0 1,+,1 0 0 0 1 1 1 0,no overflow,overflow,第3章 部分习题答案,3.1(a)0(b)0(c)1(d)probably 0(e)undefined(f)probably 0(g)1(h)probably 1,3.2(a)1(b)1(c)0(d)probably 1(e)undefined(f)probably 1(g)0(h)probably 0,3.16 A CMOS inverting gate has fewer transistors.,3.20 table 3-3 VNH=VOHmin-VIHmin=4.4-3.15=1
5、.25V(IOH=-20A)VNH=VOHmin-VIHmin=3.84-3.15=0.69V(IOH=-4mA),VNL=VILmax-VOLmax=1.35-0.1=1.34V(IOL=20A)VNL=VILmax-VOLmax=1.35-0.33=1.02V(IOL=4mA),3.21 According to figure X3.21 VNH=VOHmin-VIHmin=3.5-2.55=0.95V VNL=VILmax-VOLmax=2.35-1.5=0.85V,3.27(d),IOH=i2-i1=VOH/R2-(5-VOH)/R1=3.84/470-(5-3.84)/470=5.7
6、mA,IOL=i2-i1=VOL/R2-(5-VOL)/R1=0.33/470-(5-0.33)/470=-9.24mA,3.40 The voltage drop of resistor is:,VCC,R,LED,+,-,2V,VOL,VR=5.0-2-VOL=3-0.33=2.67V,Therefore,R=2.67V/0.005=532,3.49 Table 3-10,(a),“Excess”driving capability（剩余驱动能力）is 80A in the HIGH state.,3.49 Table 3-10,(b),“Excess”driving capability
7、（剩余驱动能力）is 140A in the HIGH state.,3.53 According to Table 3-10 VNH=VOHmin-VIHmin=2.7-2.0=0.7V VNL=VILmax-VOLmax=0.8-0.5=0.3V,3.56 Table 3-6,3-7,3-10(b)74LS driving 74HCT VNH=VOHmin-VIHmin=2.7-2.0=0.7V VNL=VILmax-VOLmax=0.8-0.5=0.3V,3.57 Table 3.6,3-7,3-10,(a)74HCT driving 74LS,“Excess”driving capab
8、ility（剩余驱动能力）is 3.8mA in the HIGH state.,第4章 部分习题答案,4.5 错误在于改变了以前的计算顺序。,(WX+YZ)=(W+X)(Y+Z),4.6(a)F=0(b)F=AB+ACE,F=ABC+ABC+ABC+ABC,4.9(c),F=(A+B+C)(A+B+C)(A+B+C)(A+B+C),F=WXY+WXY+WXY,4.9(d),F=(W+X+Y)(W+X+Y)(W+X+Y)(W+X+Y)(W+X+Y),F=XYZ+XYZ+XYZ+XYZ+XYZ,4.9(e),F=(X+Y+Z)(X+Y+Z)(X+Y+Z),F=X+YZ,4.14(a),1,1,1
9、,1,1,F=Z+XY,4.14(e),F=B+AD+ACD,4.15(b),F=XY+XZ+WYZ+WXYZ,4.15(c),F=BC+AB+ABC,YZ,WX,00 01 11 10,00011110,1,1,1,1,1,1,1,1,1,1,1,1,4.18(a),F=WXY+WYZ+WXZ+WXY,4.18(c),F=BCD+ABC+ABCD,YZ,WX,00 01 11 10,00011110,1,1,1,d,d,1,1,AB,CD,00 01 11 10,00011110,1,1,1,1,d,4.19(a),1,1,1,1,F=WX+WY+XY,4.19(c),YZ,WX,00 01
10、 11 10,00011110,1,1,1,1,1,1,1,1,F=WY+WZ+XYZ+YZ+WXY+WXZ,Static-1 hazard,Hazard-free circuit:,1,1,Static-1 hazard,Hazard-free circuit:,4.19(e),YZ,WX,00 01 11 10,00011110,0,F=(W+X+Y)(X+Z)(W+Y+Z),Static-0 hazard,Hazard-free circuit:,0,0,0,0,0,4.59(b),YZ,WX,00 01 11 10,00011110,1,1,1,1,1,1,1,YZ,WX,00 01
11、11 10,00011110,1,1,1,1,1,V=0,V=1,F=VWY+VXY+XYZ+WXYZ,4.61 The name of the circuit comes from its output equationF=2B+2B,tINV,tINV,tINV,tOR,3tINV,第6章 部分习题答案,6.9 由表6-2知，74LS00的最大tpLH和最大tpHL均为15ns，所以图X6-9的最大传播延迟为90ns。6.10 由表6-2知，74AHCT00的最大tpLH和最大tpHL均为9.0ns，所以最大传播延迟为54ns。,6.13,1IN,OUT,0,0,1,OUT=IN 1 0
12、0 1,OUT1,OUT2,OUT3,IN,OUT1,OUT2,OUT3,OUT,tpHL,tpHL,tpHL,tpLH,3tpHL+tpLH,3tpLH+tpHL,6.16 低电平有效输出的译码器要快些,(a)F=(X,Y,Z)(2,4,7),6.20,CBA,F,F=(A,B,C,D)(0,2,10,12)=ABCD+ABCD+ABCD+ABCD=(ABC+ABC+ABC+ABC)D=D(A,B,C)(0,1,5,6),6.20,D,CBA,F,F=(W,X,Y)(0,2,4,5)G=(W,X,Y)(1,2,3,6),6.20,D,G,6.21 可怕错误：某个时刻，可能有两个三态缓冲器处于
13、非悬空状态。消除错误方法：将使能信号EN_L反相后接到2G_L上。,6.28,6.29,6.47,6.47,6.51,低电平输入有效，高电平输出有效。,第6章 补充习题,1.设计一个3位奇数检测器电路，当输入为奇数时，即当 ABC=001、011，101，111时，电路输出为高电平。分别用74x151复用器和用74x138译码器实现。,解：1）用74x151实现,F=ABC+ABC+ABC+ABC=A,B,C(1,3,5,7),CBA,F,1,0,0,第6章 补充习题,解：2）用74x138实现,F=A,B,C(1,3,5,7),2.用74x151实现下面逻辑函数：1)F(A,B,C,D)=A
14、B+CD 解：F=AB(C+C)(D+D)+(A+A)(B+B)CD=ABC+ABC+ABCD+ABCD+ABCD+ABCD=ABC+ABC+ABCD+ABCD+ABCD D7=1,D6=1,D5=D D3=D D1=D D0=D2=D4=0,2.用74x151实现下面逻辑函数：2)G=(W,X,Y,Z)(0,2,4,5,7)解：G=WXYZ+WXYZ+WXYZ+WXYZ+WXYZ=WXY Z+WXY Z+WXY+WXY Z,D0=Z,D1=Z,D2=1,D3=Z D4=D5=D6=D7=0,YXW,G,Z,0,0,1,3.设计一个组合电路，当M等于0时，两个2位二进制数A=A1A0 和B=B
15、1B0实现全加；当M等于1时，两个2位二进制数实现全减。要求用两片3-8译码器74X138实现，必要时可以用门电路。,解：M=0时，A=A1A0与B=B1B0全加；M=1时，A=A1A0与B=B1B0全减；,真值表：,M A1 A0 B1 B0 S1 S0 C,0 0 0 0 0 0 0 0,0 0 0 0 1 0 1 0,0 0 0 1 0 1 0 0,0 0 0 1 1 1 1 0,0 0 1 0 0 0 1 0,0 0 1 0 1 1 0 0,M A1 A0 B1 B0 S1 S0 C,0 0 1 1 0 1 1 0,0 0 1 1 1 0 0 1,0 1 0 0 0 1 0 0,0 1
16、 0 0 1 1 1 0,0 1 0 1 0 0 0 1,0 1 0 1 1 0 1 1,0 1 1 0 0 1 1 0,0 1 1 0 1 0 0 1,0 1 1 1 0 0 1 1,0 1 1 1 1 1 0 1,1 0 0 0 0 0 0 0,1 0 0 0 1 1 1 1,M A1 A0 B1 B0 S1 S0 C,1 0 0 1 0 1 0 1,1 0 0 1 1 0 1 1,1 0 1 0 0 0 1 0,1 0 1 0 1 0 0 0,1 0 1 1 0 1 1 1,1 0 1 1 1 1 0 1,1 1 0 0 0 1 0 0,1 1 0 0 1 0 1 0,1 1 0 1 0
17、 0 0 0,1 1 0 1 1 1 1 1,1 1 1 0 0 1 1 0,1 1 1 0 1 1 0 0,M A1 A0 B1 B0 S1 S0 C,1 1 1 1 0 0 1 0,1 1 1 1 1 0 0 0,S1=M A1A0B1B0(2,3,5,6,8,9,12,15)+M A1A0B1B0(1,2,6,7,8,11,12,13),S0=A1A0B1B0(1,3,4,6,9,11,12,14),C=M A1A0B1B0(7,10,11,13,14,15)+M A1A0B1B0(1,2,3,6,8,11),B0B1A0,A1,EN_L,D0_LD7_L,D8_LD15_L,Y0Y1Y2Y3Y4Y5Y6Y7,ABC,G1G2AG2B,ABC,G1G2AG2B,U1,U2,74X138,74X138,Y0Y1Y2Y3Y4Y5Y6Y7,M,S1,4.用4位先行进位全加器74x283，将8421BCD码变为余3码。,BCD码,余3码,0 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 1,A3A2A1A0,Y3Y2Y1Y0,0 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 0 0 0 11 0 1 01 0 1 11 1 0 0,
