《集成电路的制造工艺流程课件.ppt》由会员分享，可在线阅读，更多相关《集成电路的制造工艺流程课件.ppt（105页珍藏版）》请在三一办公上搜索。
1、半导体制造工艺流程,2022/12/2,1,半导体相关知识,本征材料：纯硅 9-10个9 250000.cmN型硅： 掺入V族元素-磷P、砷As、锑SbP型硅： 掺入 III族元素镓Ga、硼BPN结：,N,P,-,-,-,-,-,-,+,+,+,+,+,2022/12/2,2,半导体元件制造过程可分为,前段（Front End）制程 晶圆处理制程（Wafer Fabrication；简称 Wafer Fab）、 晶圆针测制程（Wafer Probe）；後段（Back End） 构装（Packaging）、测试制程（Initial Test and Final Test）,2022/12/2,3
2、,一、晶圆处理制程,晶圆处理制程之主要工作为在矽晶圆上制作电路与电子元件（如电晶体、电容体、逻辑闸等），为上述各制程中所需技术最复杂且资金投入最多的过程 ，以微处理器（Microprocessor）为例，其所需处理步骤可达数百道，而其所需加工机台先进且昂贵，动辄数千万一台，其所需制造环境为为一温度、湿度与 含尘（Particle）均需控制的无尘室（Clean-Room），虽然详细的处理程序是随著产品种类与所使用的技术有关；不过其基本处理步骤通常是晶圆先经过适 当的清洗（Cleaning）之後，接著进行氧化（Oxidation）及沈积，最後进行微影、蚀刻及离子植入等反覆步骤，以完成晶圆上电路的加
3、工与制作。,2022/12/2,4,二、晶圆针测制程,经过Wafer Fab之制程後，晶圆上即形成一格格的小格 ，我们称之为晶方或是晶粒（Die），在一般情形下，同一片晶圆上皆制作相同的晶片，但是也有可能在同一片晶圆 上制作不同规格的产品；这些晶圆必须通过晶片允收测试，晶粒将会一一经过针测（Probe）仪器以测试其电气特性， 而不合格的的晶粒将会被标上记号（Ink Dot），此程序即 称之为晶圆针测制程（Wafer Probe）。然後晶圆将依晶粒 为单位分割成一粒粒独立的晶粒,2022/12/2,5,三、IC构装制程,IC構裝製程（Packaging）：利用塑膠或陶瓷包裝晶粒與配線以成積體電路
4、目的：是為了製造出所生產的電路的保護層，避免電路受到機械性刮傷或是高溫破壞。,2022/12/2,6,半导体制造工艺分类,PMOS型,双极型,MOS型,CMOS型,NMOS型,BiMOS,饱和型,非饱和型,TTL,I2L,ECL/CML,2022/12/2,7,半导体制造工艺分类,一 双极型IC的基本制造工艺：A 在元器件间要做电隔离区（PN结隔离、全介质隔离及PN结介质混合隔离） ECL（不掺金） （非饱和型） 、TTL/DTL （饱和型） 、STTL （饱和型） B 在元器件间自然隔离 I2L（饱和型）,2022/12/2,8,半导体制造工艺分类,二 MOSIC的基本制造工艺： 根据栅工艺
5、分类A 铝栅工艺B 硅 栅工艺其他分类1 、（根据沟道） PMOS、NMOS、CMOS2 、（根据负载元件）E/R、E/E、E/D,2022/12/2,9,半导体制造工艺分类,三 Bi-CMOS工艺： A 以CMOS工艺为基础 P阱 N阱 B 以双极型工艺为基础,2022/12/2,10,双极型集成电路和MOS集成电路优缺点,双极型集成电路中等速度、驱动能力强、模拟精度高、功耗比较大CMOS集成电路低的静态功耗、宽的电源电压范围、宽的输出电压幅度（无阈值损失），具有高速度、高密度潜力；可与TTL电路兼容。电流驱动能力低,2022/12/2,11,半导体制造环境要求,主要污染源：微尘颗粒、中金属
6、离子、有机物残留物和钠离子等轻金属例子。超净间：洁净等级主要由 微尘颗粒数/m3,0.1um 0.2um 0.3um 0.5um 5.0umI级 35 7.5 3 1 NA10 级 350 75 30 10 NA100级 NA 750 300 100 NA1000级 NA NA NA 1000 7,2022/12/2,12,半导体元件制造过程,前段（Front End）制程-前工序 晶圆处理制程（Wafer Fabrication；简称 Wafer Fab）,2022/12/2,13,典型的PN结隔离的掺金TTL电路工艺流程,一次氧化,衬底制备,隐埋层扩散,外延淀积,热氧化,隔离光刻,隔离扩散
7、,再氧化,基区扩散,再分布及氧化,发射区光刻,背面掺金,发射区扩散,反刻铝,接触孔光刻,铝淀积,隐埋层光刻,基区光刻,再分布及氧化,铝合金,淀积钝化层,中测,压焊块光刻,2022/12/2,14,横向晶体管刨面图,2022/12/2,15,纵向晶体管刨面图,2022/12/2,16,NPN晶体管刨面图,2022/12/2,17,1.衬底选择,P型Si 10.cm 111晶向,偏离2O5O晶圆（晶片） 晶圆（晶片）的生产由砂即（二氧化硅）开始，经由电弧炉的提炼还原成 冶炼级的硅，再经由盐酸氯化，产生三氯化硅，经蒸馏纯化后，透过慢速分 解过程，制成棒状或粒状的多晶硅。一般晶圆制造厂，将多晶硅融解
8、后，再利用硅晶种慢慢拉出单晶硅晶棒。一支85公分长，重76.6公斤的 8寸 硅晶棒，约需 2天半时间长成。经研磨、抛光、切片后，即成半导体之原料 晶圆片,2022/12/2,18,第一次光刻N+埋层扩散孔,1。减小集电极串联电阻2。减小寄生PNP管的影响,SiO2,要求：1。 杂质浓度大2。高温时在Si中的扩散系数小，以减小上推3。 与衬底晶格匹配好，以减小应力,涂胶烘烤-掩膜（曝光）-显影-坚膜蚀刻清洗去膜-清洗N+扩散(P),2022/12/2,19,外延层淀积,1。VPE（Vaporous phase epitaxy) 气相外延生长硅SiCl4+H2Si+HCl2。氧化TepiXjc+X
9、mc+TBL-up+tepi-ox,2022/12/2,20,第二次光刻P+隔离扩散孔,在衬底上形成孤立的外延层岛,实现元件的隔离.,SiO2,涂胶烘烤-掩膜（曝光）-显影-坚膜蚀刻清洗去膜-清洗P+扩散(B),2022/12/2,21,第三次光刻P型基区扩散孔,决定NPN管的基区扩散位置范围,去SiO2氧化-涂胶烘烤-掩膜（曝光）-显影-坚膜蚀刻清洗去膜清洗基区扩散(B),2022/12/2,22,第四次光刻N+发射区扩散孔,集电极和N型电阻的接触孔,以及外延层的反偏孔。AlN-Si 欧姆接触：ND1019cm-3，,去SiO2氧化-涂胶烘烤-掩膜（曝光）-显影-坚膜蚀刻清洗去膜清洗扩散,2
10、022/12/2,23,第五次光刻引线接触孔,去SiO2氧化-涂胶烘烤-掩膜（曝光）-显影-坚膜蚀刻清洗去膜清洗,2022/12/2,24,第六次光刻金属化内连线：反刻铝,SiO2,去SiO2氧化-涂胶烘烤-掩膜（曝光）-显影-坚膜蚀刻清洗去膜清洗蒸铝,2022/12/2,25,CMOS工艺集成电路,2022/12/2,26,CMOS集成电路工艺-以P阱硅栅CMOS为例,1。光刻I-阱区光刻，刻出阱区注入孔,N-Si,N-Si,SiO2,2022/12/2,27,CMOS集成电路工艺-以P阱硅栅CMOS为例,2。阱区注入及推进，形成阱区,N-Si,P-,2022/12/2,28,CMOS集成电
11、路工艺-以P阱硅栅CMOS为例,3。去除SiO2，长薄氧，长Si3N4,N-Si,P-,Si3N4,2022/12/2,29,CMOS集成电路工艺-以P阱硅栅CMOS为例,4。光II-有源区光刻,N-Si,P-,Si3N4,2022/12/2,30,CMOS集成电路工艺-以P阱硅栅CMOS为例,5。光III-N管场区光刻，N管场区注入，以提高场开启，减少闩锁效应及改善阱的接触。,光刻胶,2022/12/2,31,CMOS集成电路工艺-以P阱硅栅CMOS为例,6。光III-N管场区光刻，刻出N管场区注入孔； N管场区注入。,2022/12/2,32,CMOS集成电路工艺-以P阱硅栅CMOS为例,
12、7。光-p管场区光刻，p管场区注入， 调节PMOS管的开启电压，生长多晶硅。,2022/12/2,33,CMOS集成电路工艺-以P阱硅栅CMOS为例,8。光-多晶硅光刻，形成多晶硅栅及多晶硅电阻,多晶硅,2022/12/2,34,CMOS集成电路工艺-以P阱硅栅CMOS为例,9。光I-P+区光刻，P+区注入。形成PMOS管的源、漏区及P+保护环。,2022/12/2,35,CMOS集成电路工艺-以P阱硅栅CMOS为例,10。光-N管场区光刻，N管场区注入，形成NMOS的源、漏区及N+保护环。,2022/12/2,36,CMOS集成电路工艺-以P阱硅栅CMOS为例,11。长PSG（磷硅玻璃）。,
13、2022/12/2,37,CMOS集成电路工艺-以P阱硅栅CMOS为例,12。光刻-引线孔光刻。,2022/12/2,38,CMOS集成电路工艺-以P阱硅栅CMOS为例,13。光刻-引线孔光刻（反刻AL）。,2022/12/2,39,集成电路中电阻1,基区扩散电阻,2022/12/2,40,集成电路中电阻2,发射区扩散电阻,2022/12/2,41,集成电路中电阻3,基区沟道电阻,2022/12/2,42,集成电路中电阻4,外延层电阻,2022/12/2,43,集成电路中电阻5,MOS中多晶硅电阻,其它：MOS管电阻,2022/12/2,44,集成电路中电容1,发射区扩散层隔离层隐埋层扩散层P
14、N电容,2022/12/2,45,集成电路中电容2,MOS电容,2022/12/2,46,微电子制造工艺,2022/12/2,47,IC常用术语,圆片：硅片芯片(Chip, Die)：6、8 ：硅（园）片直径：1 25.4mm6150mm; 8200mm; 12300mm; 亚微米1m的设计规范深亚微米=0.5 m的设计规范0.5 m 、 0.35 m 设计规范（最小特征尺寸）布线层数：金属（掺杂多晶硅）连线的层数。集成度：每个芯片上集成的晶体管数,2022/12/2,48,IC工艺常用术语,净化级别：Class 1, Class 10, Class 10,000每立方米空气中含灰尘的个数去离
15、子水氧化扩散注入光刻.,2022/12/2,49,生产工厂简介,PSI,2022/12/2,50,Fab Two was completed January 2, 1996 and is a State of the Art facility. This 2,200 square foot facility was constructed using all the latest materials and technologies. In this set of cleanrooms we change the air 390 times per hour, if you do the ma
16、th with ULPA filtration this is a Class One facility. We have had it tested and it does meet Class One parameters (without any people working in it). Since we are not making microprocessors here and we dont want to wear space suits, we run it as a class 10 fab. Even though it consistently runs well
17、below Class Ten.,一级净化厂房,2022/12/2,51,Here in the Fab Two Photolithography area we see one of our 200mm .35 micron I-Line Steppers. this stepper can image and align both 6 & 8 inch wafers.,光刻区域,亚微米级光刻机,2022/12/2,52,Another view of one of the Fab Two Photolithography areas.,2022/12/2,53,Here we see a
18、technician loading 300mm wafers into the SemiTool. The wafers are in a 13 wafer Teflon cassette co-designed by Process Specialties and SemiTool in 1995. Again these are the worlds first 300mm wet process cassettes (that can be spin rinse dried).,花篮,2022/12/2,54,As we look in this window we see the W
19、orlds First true 300mm production furnace. Our development and design of this tool began in 1992, it was installed in December of 1995 and became fully operational in January of 1996.,熔炉,2022/12/2,55,Here we can see the loading of 300mm wafers onto the Paddle.,2022/12/2,56,Process Specialties has de
20、veloped the worlds first production 300mm Nitride system! We began processing 300mm LPCVD Silicon Nitride in May of 1997.,2022/12/2,57,2,500 additional square feet of State of the Art Class One Cleanroom is currently processing wafers! With increased 300mm & 200mm processing capabilities including m
21、ore PVD Metalization, 300mm Wet processing / Cleaning capabilities and full wafer 300mm .35um Photolithography, all in a Class One enviroment.,净化厂房,2022/12/2,58,Currently our PS300A and PS300B diffusion tools are capable of running both 200mm & 300mm wafers. We can even process the two sizes in the
22、same furnace load without suffering any uniformity problems! (Thermal Oxide Only),扩散,2022/12/2,59,Accuracy in metrology is never an issue at Process Specialties. We use the most advanced robotic laser ellipsometers and other calibrated tools for precision thin film, resistivity, CD and step height m
23、easurement. Including our new Nanometrics 8300 full wafer 300mm thin film measurement and mapping tool. We also use outside laboratories and our excellent working relationships with our Metrology tool customers, for additional correlation and calibration.,光刻间,2022/12/2,60,One of two SEM Labs located
24、 in our facility. In this one we are using a field emission tool for everything from looking at photoresist profiles and measuring CDs to double checking metal deposition thicknesses. At the helm, another one of our process engineers you may have spoken with Mark Hinkle.,检测,2022/12/2,61,Here we are
25、looking at the Incoming material disposition racks,材料间,2022/12/2,62,Above you are looking at a couple of views of the facilities on the west side of Fab One. Here you can see one of our 18.5 Meg/Ohm DI water systems and one of four 10,000 CFM air systems feeding this fab (left picture), as well as o
26、ne of our waste air scrubber units (right picture). Both are inside the building for easier maintenance, longer life and better control.,2022/12/2,63,集成电路（Integrated Circuit, IC）：半导体IC，膜IC，混合IC半导体IC：指用半导体工艺把电路中的有源器件、无源元件及互联布线等以相互不可分离的状态制作在半导体上，最后封装在一个管壳内，构成一个完整的、具有特定功能的电路。,半导体IC,双极IC,MOSIC,BiCMOS,PM
27、OS IC,CMOS IC,NMOS IC,2022/12/2,64,MOS IC及工艺,MOSFET Metal Oxide Semiconductor Field Effect Transistor . 金属氧化物半导体场效应晶体管,Si,金属,氧化物（绝缘层、SiO2）,半导体,MOS(MIS)结构,2022/12/2,65,栅氧化层厚度：50埃1000埃（5nm100nm）VT阈值电压电压控制,N沟MOS（NMOS）,P型衬底，受主杂质； 栅上加正电压，表面吸引电子，反型，电子通道； 漏加正电压，电子从源区经N沟道到达漏区，器件开通。,2022/12/2,66,N衬底,p+,p+,漏,
28、源,栅,栅氧化层,场氧化层,沟道,P沟MOS（PMOS）,VT,VGS,ID,+,-,VDS 0,N型衬底，施主杂质，电子导电； 栅上加负电压，表面吸引空穴，反型，空穴通道； 漏加负电压，空穴从源区经P沟道到达漏区，器件开通。,2022/12/2,67,CMOS,CMOS：Complementary Symmetry Metal Oxide Semiconductor 互补对称金属氧化物半导体特点：低功耗,VSS,VDD,Vo,Vi,CMOS倒相器,PMOS,NMOS,I/O,I/O,VDD,VSS,C,C,CMOS传输门,2022/12/2,68,N-Si,P+,P+,n+,n+,P-阱,D
29、,D,Vo,VG,VSS,S,S,VDD,CMOS倒相器截面图,CMOS倒相器版图,2022/12/2,69,A NMOS Example,2022/12/2,70,pwell,PwellActivePolyN+ implantP+ implantOmicontactMetal,2022/12/2,71,Ntype Si,SiO2,光刻胶,MASK Pwell,2022/12/2,72,Ntype Si,SiO2,光刻胶,光刻胶,MASK Pwell,2022/12/2,73,Ntype Si,SiO2,光刻胶,光刻胶,SiO2,2022/12/2,74,Ntype Si,SiO2,SiO2,
30、Pwell,2022/12/2,75,pwell,PwellActivePolyN+ implantP+ implantOmicontactMetal,2022/12/2,76,Ntype Si,SiO2,Pwell,SiO2,光刻胶,MASK active,MASK Active,Si3N4,2022/12/2,77,Ntype Si,SiO2,Pwell,SiO2,光刻胶,光刻胶,MASK active,MASK Active,Si3N4,2022/12/2,78,Ntype Si,SiO2,Pwell,SiO2,光刻胶,光刻胶,Si3N4,2022/12/2,79,Ntype Si,Si
31、O2,Pwell,SiO2,场氧,场氧,场氧,Pwell,Si3N4,2022/12/2,80,Ntype Si,SiO2,Pwell,场氧,场氧,场氧,Pwell,2022/12/2,81,Ntype Si,SiO2,Pwell,SiO2,场氧,场氧,场氧,Pwell,poly,2022/12/2,82,active,pwell,PwellActivePolyN+ implantP+ implantOmicontactMetal,2022/12/2,83,Ntype Si,SiO2,Pwell,SiO2,MASK poly,场氧,场氧,场氧,Pwell,poly,光刻胶,2022/12/2,
32、84,Ntype Si,SiO2,Pwell,SiO2,MASK poly,场氧,场氧,场氧,Pwell,光刻胶,poly,2022/12/2,85,Ntype Si,SiO2,Pwell,SiO2,场氧,场氧,场氧,Pwell,poly,2022/12/2,86,Ntype Si,SiO2,Pwell,SiO2,场氧,场氧,场氧,Pwell,poly,2022/12/2,87,active,pwell,poly,PwellActivePolyN+ implantP+ implantOmicontactMetal,2022/12/2,88,Ntype Si,SiO2,Pwell,SiO2,MA
33、SK N+,场氧,场氧,场氧,Pwell,poly,光刻胶,2022/12/2,89,Ntype Si,SiO2,Pwell,SiO2,场氧,场氧,场氧,Pwell,光刻胶,poly,N+ implant,2022/12/2,90,active,pwell,poly,P+ implant,PwellActivePolyN+ implantP+ implantOmicontactMetal,2022/12/2,91,Ntype Si,SiO2,Pwell,SiO2,MASK N+,场氧,场氧,场氧,Pwell,poly,光刻胶,光,2022/12/2,92,2022/12/2,93,2022/12/2,94,2022/12/2,95,2022/12/2,96,2022/12/2,97,外延生长,2022/12/2,98,隔离层扩散,2022/12/2,99,基区扩散,2022/12/2,100,发射极扩散,2022/12/2,101,氧化,2022/12/2,102,接触孔,2022/12/2,103,金属层,2022/12/2,104,定型金属层,2022/12/2,105,
