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1、Modern Semiconductor Devices for Integrated Circuits (C. Hu),Slide 7-1,Chapter 7 MOSFETs in ICs Scaling, Leakage, and Other Topics,7.1 Technology Scaling - for Cost, Speed, and Power ConsumptionNew technology node every two years or so. Defined by minimum line width-spacing average. Feature sizes ar
2、e 70% of previous nodes. Reduction of circuit area by 2 good for cost and speed.,Modern Semiconductor Devices for Integrated Circuits (C. Hu),Slide 7-2,International Technology Roadmap for Semiconductors,Vdd is reduced at each node to contain power consumption in spite of rising transistor density a
3、nd frequency Tox is reduced to raise Ion and retain good transistor behaviors HP: High performance; LSTP: Low stand-by power,Modern Semiconductor Devices for Integrated Circuits (C. Hu),Slide 7-3,7.1.2 Strained Silicon: example of innovations,The electron and hole mobility can be raised by carefully
4、 designed mechanical strain.,N-type Si,Trenches filled with epitaxial SiGe,Gate,S,D,Mechanical strain,Modern Semiconductor Devices for Integrated Circuits (C. Hu),Slide 7-4,7.2 Subthreshold Current,The leakage current that flows at VgVt is called the subthreshold current.,90nm technology. Gate lengt
5、h: 45nm,The current at Vgs=0 and Vds=Vdd is called Ioff.,Intel, T. Ghani et al., IEDM 2003,Modern Semiconductor Devices for Integrated Circuits (C. Hu),Slide 7-5,Subthreshold current ns (surface inversion carrier concentration)ns eqs/kT,s varies with Vg through a capacitor network,In subthreshold, s
6、 = constant +Vg/h,Modern Semiconductor Devices for Integrated Circuits (C. Hu),Slide 7-6,Subthreshold Leakage Current,Subthreshold current changes 10 x for h60mV change in Vg. Reminder: 60mV is (ln10)kT/q,Subthreshold swing, S : the change in Vgs corresponding to 10 x change in subthreshold current.
7、 S = h60mV, typically 80-100mV,Modern Semiconductor Devices for Integrated Circuits (C. Hu),Slide 7-7,Subthreshold Leakage Current,is determined only by Vt and subthreshold swing.,Practical definition of Vt : the Vgs at which Ids= 100nAW/L=,1/S,Modern Semiconductor Devices for Integrated Circuits (C
8、. Hu),Slide 7-8,Subthreshold Swing,Smaller S is desirable (lower Ioff for a given Vt). Minimum possible value of S is 60mV/dec.How do we reduce swing?Thinner Tox = larger Coxe Lower substrate doping = smaller Cdep Lower temperatureLimitationsThinner Tox oxide breakdown reliability or oxide leakage c
9、urrent Lower substrate doping doping is not a free parameter but set by Vt.,Modern Semiconductor Devices for Integrated Circuits (C. Hu),Slide 7-9,Effect of Interface States on Subthreshold Swing,Interface states may be filled by electrons or empty depending on its energy relative to EF, i.e., depen
10、ding on Vg.dQint/d (number or interface state per eV-cm2) presents another capacitance in parallel with Cdep,Modern Semiconductor Devices for Integrated Circuits (C. Hu),Slide 7-10,7.3 Vt Roll-off,65nm technology. EOT=1.2nm, Vdd=1V,K. Goto et al., (Fujitsu) IEDM 2003,Vt roll-off: Vt decreases with d
11、ecreasing Lg. It determines the minimum acceptable Lg because Ioff is too large if Vt becomes too small.,Question: Why data is plotted against Lg, not L? Answer: L is difficult to measure. Lg is. Also, Lg is the quantity that manufacturing engineers can control directly.,Modern Semiconductor Devices
12、 for Integrated Circuits (C. Hu),Slide 7-11,Why Does Vt Decrease with L? Potential Barrier Concept,When L is small, smaller Vg is needed to reduce the barrier to 0.2V, i.e. Vt is smaller.Vt roll-off is greater for shorter L,Modern Semiconductor Devices for Integrated Circuits (C. Hu),Slide 7-12,Vds
13、dependence,Energy-Band Diagram from Source to Drain,L dependence,Modern Semiconductor Devices for Integrated Circuits (C. Hu),Slide 7-13,Vt Roll-off Simple Capacitance Model,As the channel length is reduced, drain to channel distance is reduced Cd increases,Vds helps Vgs to invert the surface, there
14、fore,Due to built-in potential between N- channel and N+ drain & source,2-D Poisson Eq. solution shows that Cd is an exponential function of L.,Modern Semiconductor Devices for Integrated Circuits (C. Hu),Slide 7-14,Vertical dimensions (Tox, Wdep, Xj) must be scaled to support L reduction,Modern Sem
15、iconductor Devices for Integrated Circuits (C. Hu),Slide 7-15,7.4 Reducing Gate-Insulator Electrical Thickness and Tunneling Leakage,Oxide thickness has been reduced over the years from 300nm to 1.2nm.Why reduce oxide thickness?Larger Cox to raise IonReduce subthreshold swingControl Vt roll-offThinn
16、er is better. However, if the oxide is too thinBreakdown due to high fieldLeakage current,Modern Semiconductor Devices for Integrated Circuits (C. Hu),Slide 7-16,Gate Tunneling Leakage Current,For SiO2 films thinner than 1.5nm, tunneling leakage current has become the limiting factor. HfO2 has sever
17、al orders lower leakage for the same EOT.,Modern Semiconductor Devices for Integrated Circuits (C. Hu),Slide 7-17,Replacing SiO2 with HfO2-High-k Dielectric,HfO2 has a relative dielectric constant (k) of 24, six times large than that of SiO2. For the same EOT, the HfO2 film presents a much thicker (
18、albeit a lower) tunneling barrier to the electrons and holes. Toxe can be further reduced by introducing metal-gate technology since the poly-depletion effect is eliminated.,(After W. Tsai et al., IEDM03),Modern Semiconductor Devices for Integrated Circuits (C. Hu),Slide 7-18,Challenges of High-K Te
19、chnology,The difficulties of high-k dielectrics:chemical reactions between them and the silicon substrate and gate,lower surface mobility than the Si/SiO2 systemtoo low a Vt for P-channel MOSFET (as if there is positive charge in the high-k dielectric). long-term reliability,A thin SiO2 interfacial
20、layer may be inserted between Si-substrate and high-k film.,Question: How can Tinv be reduced? (Answer is in Sec. 7.4 text),Modern Semiconductor Devices for Integrated Circuits (C. Hu),Slide 7-19,7.5 How to Reduce Wdep,Or use retrograde doping with very thin lightly doped surface layerAlso, less imp
21、urity scattering in the inversion layer higher mobility,Wdep can be reduced by increasing Nsub,If Nsub is increased, Cox has to be increased in order to keep Vt the same. Wdep can be reduced in proportion to Tox.,Modern Semiconductor Devices for Integrated Circuits (C. Hu),Slide 7-20,7.5 Ideal Retro
22、grade Doping Profile,Compared with uniformly doped body,Assume the body is heavily doped with an undoped layer, Trg thick, at the surface.,Ideal retrograde doping yields a depletion region width (Trg) half as thick as Wdep of a uniform doped body.,Modern Semiconductor Devices for Integrated Circuits
23、 (C. Hu),Slide 7-21,7.6 Shallow Junction and Metal Source/Drain,The shallow junction extension helps to control Vt roll-off.Shallow junction and light doping combine to produce an undesirable parasitic resistance that reduces the precious Ion. Theoretically, metal S/D can be used as a very shallow “
24、junction”.,Modern Semiconductor Devices for Integrated Circuits (C. Hu),Slide 7-22,7.6.1 MOSFET with Metal Source/Drain,To unleash the potentials of Schottky S/D MOSFET, a low- Schottky junction is needed for NFETs and low- for PFET.,Modern Semiconductor Devices for Integrated Circuits (C. Hu),Slide
25、 7-23,7.7 Variations and Design for Manufacturing,Higher Ion goes hand-in-hand with larger Ioff - think L, Vt, Tox, Vdd.Figure shows spread in Ion (and Ioff) produced by intentional difference in Lg and unintentional manufacturing variatons in Lg and other parameters.,NMOS,PMOS,Intel, T. Ghani et al
26、., IEDM 2003,Modern Semiconductor Devices for Integrated Circuits (C. Hu),Slide 7-24,Variation Tolerant Circuit Design,Multiple Vt Lower Vt is used only in the blocks that need speedMultiple Vdd Higher Vdd is used only in the blocks that need speedSubstrate (well) biasOnly some circuit blocks need t
27、o operate at high speed.Can use reverse well bias to raise the Vt for the rest.This techniques can also reduce the chip-to-chip and block-to-block variations with intelligent control circuitry.Would like larger body effect than conventional MOSFET.,Modern Semiconductor Devices for Integrated Circuit
28、s (C. Hu),Slide 7-25,7.8 Ultra-Thin-Body SOI and Multigate MOSFETs,Reducing Tox gives the gate excellent control of Si surface potential. But, the drain could still have more control than the gate along sub-surface leakage current paths. (Right figure.),Modern Semiconductor Devices for Integrated Ci
29、rcuits (C. Hu),Slide 7-26,7.8.1 Ultra-Thin-Body MOSFET and SOI,UTB MOSFET built on ultra thin silicon film on an insulator (SiO2).Since the silicon film is very thin, perhaps less than 10nm, no leakage path is very far from the gate.,Source,Drain,TSi = 3 nm,Gate,SiO2,Si,Electron Micrograph of UTB MO
30、SFET,Modern Semiconductor Devices for Integrated Circuits (C. Hu),Slide 7-27,Ultra-Thin-Body MOSFET,The subthreshold leakage is reduced as the silicon film is made thinner.,Tox=1.5nm, Nsub=1e15cm-3, Vdd=1V, Vgs=0,Modern Semiconductor Devices for Integrated Circuits (C. Hu),Slide 7-28,Producing Silic
31、on-on-Insulator (SOI) Substrates,Initial Silicon wafer A and BOxidize wafer A to grow SiO2Implant hydrogen into wafer APlace wafer A, upside down, over wafer B. A low temperature annealing causes the two wafers to fuse together.Apply another annealing step to for H2 bubbles and split wafer A.Polish
32、the surface and the SOI wafer is ready for use. Wafer A can be reused.,Modern Semiconductor Devices for Integrated Circuits (C. Hu),Slide 7-29,Cross-Section of SOI Circuits,Due to the high cost of SOI wafers, only some microprocessors, which command high prices and compete on speed, have embraced th
33、is technology. In order to benefit from the UTB concept, Si film thickness must be agreesively reduced to Lg/4,Modern Semiconductor Devices for Integrated Circuits (C. Hu),Slide 7-30,7.8.2 Multi-gate MOSFET and FinFET,The second way of eliminating deep leakage paths is to provide gate control from m
34、ore than one side of the channel.The Si film is very thin so that no leakage path is far from one of the gates. Because there are more than one gates, the structure may be called multi-gate MOSFET.,double-gate MOSFET,Modern Semiconductor Devices for Integrated Circuits (C. Hu),Slide 7-31,FinFET,One
35、multi-gate structure, called FinFET, is particularly attractive for its simplicity of fabrication.The channel consists of the two vertical surfaces and the top surface of the fin. Question: What is the channel width, W?Answer: The sum of twice the fin height and the width of the fin.,SOI FinFET,Bulk
36、 FinFET,Modern Semiconductor Devices for Integrated Circuits (C. Hu),Slide 7-32,Variations of FinFET,Nanowire FinFET,Short FinFET,Tall FinFET,Tall FinFET has the advantage of providing a large W and therefore large Ion while occupying a small footprint. Short FinFET has the advantage of less challen
37、ging lithography and etching. Nanowire FinFET gives the gate even more control over the silicon wire by surrounding it.,Modern Semiconductor Devices for Integrated Circuits (C. Hu),Slide 7-33,I-V of a Nanowire “Multi-Gate” MOSFET,Modern Semiconductor Devices for Integrated Circuits (C. Hu),Slide 7-3
38、4,What Parameters Determine the gds ?,A larger L or smaller ld , i.e. smaller Tox, Wdep, Xj, can increase the maximum voltage gain.The cause is “Vt dependence on Vds”in short channel transistors.,and,Idsat is a function of Vgs-Vt,(From Eq. 7.3.3, ),7.9 Output Conductance,Modern Semiconductor Devices
39、 for Integrated Circuits (C. Hu),Slide 7-35,Channel Length Modulation,For large L and Vds close to Vdsat, another mechanism may dominate gds. That is channel length modulation.Vds-Vdsat, is dissipated over a short distance next to drain, causing the “channel length” to decrease. More with increasing
40、 Vds.,Modern Semiconductor Devices for Integrated Circuits (C. Hu),Slide 7-36,7.10 Device and Process Simulation,Device SimulationCommercially available computer simulation tools can solve all the equations presented in this book simultaneously with few or no approximations. Device simulation provid
41、es quick feedback about device design before long and expensive fabrication. Process SimulationInputs to process simulation: lithography mask pattern, implantation dose and energy, temperatures and times for oxidization and annealing steps, etc. The process simulator generates a 2-D or 3-D structure
42、s with all the deposited or grown and etched thin films and doped regions. This output may be fed into a device simulator as input together with applied voltages.,Modern Semiconductor Devices for Integrated Circuits (C. Hu),Slide 7-37,Example of Process Simulation,FinFET Process,Manual, Taurus Proce
43、ss, Synoposys Inc.,The small figures only show 1/4 of the complete FinFET-the quarter farthest from the viewer.,Modern Semiconductor Devices for Integrated Circuits (C. Hu),Slide 7-38,Example of Device Simulation-Density of Inversion Charge in the Cross-Section of a FinFET Body,The inversion layer h
44、as a significant thickness (Tch).There are more more subthreshold inversion electrons at the corners.,Modern Semiconductor Devices for Integrated Circuits (C. Hu),Slide 7-39,7.11 MOSFET Compact Modeling for Circuit Simulation,For circuit simulation, MOSFETs are modeled with analytical equations. Dev
45、ice model is the link between technology/manufacturing and design/product. The other link is design rules.Circuits are designed A. through circuit simulations or B. using cell libraries that have been carefully designed beforehand using circuit simulations. BSIM is the first industry standard MOSFET
46、 model. It contains all the models presented in these chapters and more.,Modern Semiconductor Devices for Integrated Circuits (C. Hu),Slide 7-40,Examples of BSIM Model Results,Modern Semiconductor Devices for Integrated Circuits (C. Hu),Slide 7-41,Example of BSIM Model Results,Modern Semiconductor D
47、evices for Integrated Circuits (C. Hu),Slide 7-42,Example of BSIM Model Results,Modern Semiconductor Devices for Integrated Circuits (C. Hu),Slide 7-43,7.12 Chapter Summary,The major component of Ioff is the subthreshold current,Vt decreases with L, a fact known as Vt roll-off, caused by drain-induced barrier lowering (DIBL).,Output conductance of short channel transistors,
