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1、面向二十一世纪的嵌入式系统设计技术,第八讲：,嵌入式项目开发过程,Embedded System Project Management,主讲教员：徐欣,国防科大电子科学与工程学院嵌 入 式 系 统 开 放 研 究 小 组,主要内容,嵌入式设计生命周期选择过程划分决策,详细的硬件与软件设计,嵌入式硬件开发过程嵌入式软件开发过程软硬件协同设计过程,开发、调试环境与工具,嵌入式项目设计的各个阶段（图）,嵌入式项目设计的七个具体阶段,产品定义,软件与硬件的划分迭代与实现,详细的硬件与软件设计硬件与软件集成产品测试与发布持续维护与升级,嵌入式项目开发过程中使用的工具,参见PDF文档中的Figure 1.
2、2,嵌入式项目设计生命周期（一）产品定义,工程师追求卓越的功能和性能,浪费时间和资源,决策层早期一般不允许工程师接触客户,损失了一些有用的建议和观点,理想的客户研究访问,首席：市场营销；第二成员：记录与提问其他技术人员：参与探讨并形成产品蓝图,列出必做适宜清单，找到设计产品的共同蓝图,嵌入式项目设计生命周期（二）硬件与软件的划分,观点：软硬件是可以互相替换的,如：浮点运算与浮点处理器（FPU）等,两种不同的划分策略,优化处理器能力和软件,通过ASIC设计找到解决途径,划分中需要考虑的许多需求,价格低、性能领先、市场竞争、知识产权等,CPU的选择将影响划分决策和开发工具选择,嵌入式项目设计生命周
3、期（三）迭代与实现,迭代与实现阶段的主要特点：,主要障碍可能还是在软硬件的详细划分上设计约束被深刻理解和建模保留软硬件划分之间的余地,软硬件设计人员之间的迭代,结构体系模拟器：Simulator,评估板或开发板：Evaluation Board目的：减小设计阶段后期风险,嵌入式项目设计生命周期（四）,详细的硬件与软件设计文档管理,这里不详细讨论软硬件设计问题,大部分同学在其他课程中学到的C/C+/JAVA编程技术、数字设计和微处理器知识使他们有足够的机会解决设计中遇到的问题,文档管理与质量控制,设计复用和可视化减小设计修改成本,有助于测试和质量控制,嵌入式项目设计生命周期（五）硬件与软件集成,
4、Not a easy Problem,Big Endian/Little Endian引发的问题,调试过程及实时系统调试方法带来的一些问题等,嵌入式系统设计中软硬件集成的颠峰状态,由第一个硬件原型、应用软件、驱动代码、操作系统设计出完美的系统没有致命错误没有飞线,不用重新设计ASIC或FPGA没有太多的软件设计修改,嵌入式项目设计生命周期（六）产品测试与发布,嵌入式产品测试具有特殊的意义,人们或许可以容忍PC偶然死机，但是核电站报警系统？！导弹控制系统？！,PC外围硬件Is there any problem with you?,测试的目的,不仅是确信软件不会在关键时刻崩馈,还必须查明是否在运
5、行时能接近最优性能，尤其是用高级语言编写或多个开发人员编写的程序,每个微小的错误都可能是致命的,如轻微内存泄漏，长时间运行才能发现的问题等,嵌入式项目设计生命周期（七）产品维护和升级,产品维护的模式,维护/支持小组！设计小组,维护详细文档经验技巧上一代产品,产品升级的巨大代价,理解原设计人员的思路与代码,反向逆推并改进原始设计小组的工作需要非凡的技艺或强大的反向设计工具,否则，不如开始新的设计，这是原供应商和生产上所不愿意看到的,主要内容,嵌入式设计生命周期选择过程划分决策,详细的硬件与软件设计,嵌入式硬件开发过程嵌入式软件开发过程软硬件协同设计过程,开发、调试环境与工具,选择过程处理器平台,
6、选择处理器是一个复杂的工作，它不仅是一个简单的“优化”问题，必须通过四道关键测试：,是否便于实现,是否能够提供足够的性能是否有合适的操作系统支持,是否有大量合适的开发工具（和设计资源）支持,其他因素可能会影响这种选择,上市时间、企业对特定开发商的偏好或承诺等,How do we choose microprocessor?,Cost ofGoods,Real-timeConstraints,LegacyCode,PowerBudget,PerformanceTime toMarket,Landmines,ToolSupport,Clock SpeedBrute force method of
7、improving performanceBottleneck could be in software design orcompiler!Faster isnt always betterPerformance Clock speedTrade-off:,As clock speed,energy,Memory costs increaseOther peripheral devices will cost more,Evaluating processor performance,Clock speed:but instructions per cycle may differInstr
8、uctions/sec:but work per instruction maydiffer,Dhrystone:Synthetic benchmark,developed in1984,SPEC:realistic benchmarks,but oriented todesktops,EEMBC EDN Embedded Benchmark Consortium,www.eembc.org,Suites of benchmarks:automotive,consumerelectronics,networking,office automation,telecommunications,PC
9、,IR,von Neumann Architectureaddress,memory,data,200CPU,200,ADD r5,r1,r3,ADD r5,r1,r3,Harvard architectureaddress,data memoryprogram memory,dataaddressdata,PCCPU,von Neumann vs.Harvard,Harvard cant use self-modifying code.Harvard allows two simultaneous memoryfetches.,Most DSP use Harvard architectur
10、e forstreaming data:,greater memory bandwidth;more predictable bandwidth.,ARM vs.SHARC,ARM7 is von Neumann architecture,We will concentrate on ARM7,ARM9 is Harvard architecture,SHARC is modified Harvard architecture.,On chip memory(1Gbit)evenly split betweenprogram memory(PM)and data memory(DM)Progr
11、am memory can be used to store some data.Allows data to be fetched from both memory in parallel,uP Performance,Width of data path,performance(Width of Data Path)2,The most general categorization of processor performanceTypical data bus widths:4,8,16,32,64,128 bits wideWider data busses-greater data
12、processing capabilityData bus width trade-off,the wider data path:,Is more complex to design,Takes up more room on PC boardsGenerates greater amounts of energyRequires more costly memory designsIs not compatible with existing hardware,More on data path width,Data path width generally determines func
13、tionality4,8 bits-Appliances,modems,simple applications16 bits-Industrial controllers,automotive,32 bits-Telecomm,laser printers,high-performance apps64 bits-PCs,UNIX workstations,games128,256 bits(VLIW)-Next generation,Internal and external data paths may differ in size,Narrower memory is more econ
14、omicalMC68000:32-bit internal/16-bit externalMC68008:32-bit internal/8-bit external80C188:16-bit internal/8-bit external,Remember:An 8-bit processor can do almost everything a 64-bitprocessor can do,it will just take longer to accomplish,Processor Micro-architecture,On-chip instruction/data cache,ho
15、w big?Pipelines,Superscalar/VLIW,Trade-off-high performance costs money,powerAddress bus design,Address bus width:16-36 bits,Multiplexed,synchronous,asynchronous,Processor type:CISC,RISC,DSP,What is the nature of the algorithm to implement?Control rich:CISCData rich:RISC,Data transforms and mathemat
16、ical processing:DSP,More on address bus width,The amount of externally accessible memory is defined asthe Address Space of the processor,Can vary from 1KB for simple microcontrollers to over 60 GBin high performance processors,Size of the address space doesnt mean that you have thatmuch memory,it on
17、ly means that the capabilities exist todirectly access it,Processors with smaller address spaces can still manipulatelarger memory arrays with techniques such as PagingSpecial memory or I/O location used to swap in and outmemory pages,Example:An 8-bit Z80 processor with a 16-bit addressbus(64K)can a
18、ddress a 1Mbyte address space byswapping between one of 16,64Kbyte,memory pages,Single or Multiple processors,Combine CISC,RISC and DSP in a singledesign,Tight coupling or loose couplingArchitecture,Code design,compiler capabilitiesDebug tool availabilitySystem simulation tools,Integration of functi
19、ons,Microprocessor or microcontroller?Review:,A microprocessor contains the basic CPU functionality,and moreA microcontroller combines the CPU core with peripheral devicesThe microprocessor is usually the leading edge of performance,Lowest level of integrationHighest cost,Higher levels of integratio
20、n imply,Lower system costsGreater reliabilityLess powerFaster,Higher processor cost,As uP matures the core moves into the uC families,CPU CoreRAMROMFLASHTimersWatchdog,CoprocessorLCD Controller,DMACSSAP490B$100KNRE,FLASHPCI BusBridge,Real-timeClockCacheA/D ConverterSerial PortsEthernetParallel Ports
21、,主要内容,嵌入式设计生命周期选择过程划分决策,详细的硬件与软件设计,嵌入式硬件开发过程嵌入式软件开发过程软硬件协同设计过程,开发、调试环境与工具,划分决策,软件与硬件的双重性,软件与硬件的分离：基于开发成本和性能的决策,新的硬件描述语言：HDLHandel-C协同设计过程,Hardware/Software Partitioning,Definition,The process of deciding,for each subsystem,whetherthe required functionality is more advantageouslyimplemented in hardwa
22、re or software,Goal,To achieve a partition that will give us the requiredperformance within the overall system requirements(insize,weight,power,cost,etc.),This is a multivariate optimization problem thatwhen automated,is an NP-hard problem,HW/SW Partitioning Issues,Partitioning into hardware and sof
23、tware affectsoverall system cost and performanceHardware implementation,Provides higher performance via hardwarespeeds and parallel execution of operationsIncurs additional expense of fabricating ASICs,Software implementation,May run on high-performance processors at lowcost(due to high-volume produ
24、ction),Incurs high cost of developing and maintaining(complex)software,Partitioning Approaches,Start with all functionality in software and moveportions into hardware which are time-critical andcan not be allocated to software(software-oriented partitioning),Start with all functionality in hardware
25、and moveportions into software implementation(hardware-oriented partitioning),主要内容,嵌入式设计生命周期选择过程划分决策,详细的硬件与软件设计,嵌入式硬件开发过程嵌入式软件开发过程软硬件协同设计过程,开发、调试环境与工具,软硬件设计过程中的文档管理,需求分析文档（产品定义阶段）,总体方案设计（选择过程和软硬件划分）概要设计文档（软硬件初步设计）详细设计文档（软硬件详细设计）,测试需求文档（模块测试及联调准备）系统测试报告（测试小组）使用说明文档/源程序注释,总体方案设计,项目概述（来自需求分析文档）,功能与指标描述
26、（来自需求分析文档）系统外部接口描述,系统软硬件设计框架（选择过程和划分决策）软硬件模块化设计概要,功能、接口,时间与进度安排（甘特图）产品成本估算研制经费需求,甘特图任务,技术方案设计系统软件构建,系统联调、设计验证BSP及设备驱动程序,春节,产品现场测试,原理图及PCB设计,PCB制板及硬件调试,设计完善,IP Core及FPGA设计与仿真时间,2002/12/1,2003/1/1,2003/2/1,2003/3/1,2003/4/1,2003/5/1,图4 项目研制进度与计划安排,模块化设计,功能描述,接口描述：硬件接口与软件参数设计流图,自然语言流程框图原理框图状态流图,UML：统一建
27、模描述语言,状态流图软硬件统一描述方式,Memo Button,Turn on theWarning,Reset Warning,Turnoff the,warningMessagecounter=24,Check thenumber ofmessages,Message=1-23,24-29,Generatememory addressand recordmessage&inc,message counterMemoryPage is fullMessage,Counter=30,Delete the first,message anddecrement,Hang Up,messagecou
28、nterState Diagram of Recording a Message,主要内容,嵌入式设计生命周期选择过程划分决策,详细的硬件与软件设计,嵌入式硬件开发过程嵌入式软件开发过程软硬件协同设计过程,开发、调试环境与工具,嵌入式软件开发环境,SourceListing,SourceListing,Create UserLibrary(optional),Librarian,C or C+Source File,C or C+Compiler,AssemblySource File,Assembler,RelocatableObjectModule,UserLibrary,IncludeF
29、iles,LibraryDirectoryListing,LinkerCommandFileDeviceProgrammer,Absolute,Relocatable,Object,Linker,Object,Target,Module,Module,DevelopmentSystemLink Map,Debugging Toolset,Instruction Set Simulator(ISS)Debug MonitorROM EmulatorLogic Analyzer,In-Circuit Emulator(ICE),Joint Test Action Group(JTAG),Debug
30、ging embedded systems,Challenges:,target system may be hard to observe;target may be hard to control;,may be hard to generate realistic inputs;setup sequence may be complex.,Instruction Level Simulator,Host based software that simulates the,functionality and instruction set of the targetprocessorTwo
31、 types,Functionality-accurate,Implements only instruction set,Cycle-accurate,Maintain cycle-by-cycle accuracy of processor,including cache,pipeline,and memory behavior,Useful in early stage of the projectDisadvantage:,No simulation of peripherals,Remote Debugger,Front-end runs on host computer andpr
32、ovides user interface,Backend runs on target processor andcommunicates with the front-end overcommunication link,Backend is known as debug monitor andprovides low level control of targetprocessor,Debug monitor,A monitor program residing on the target ROMprovides basic debugger functions,Read registe
33、r xModify register y,Read n bytes of memory starting at addressModify data at addressRun to breakpointSingle stepLoad code,Debugger should have minimal footprint inmemory.,User program must be careful not to destroydebugger program,Debug monitor(Contd.),HOST-BASED DEBUGGER PROGRAM-Knowledge of sourc
34、e files-Knowledge of object files,SYSTEM ROMCODE PARTITION,Symbol Table Cross reference files,Power onreset codeSerial Port,0 xFFFFF,3,2,ISRDebugKernel,2,1,ApplicationProgramSoftware,0 1,debug trapvectorSERIAL COMM LINKSerial PortInt.Vector0 x000000,Debug monitors:Advantages,Low cost:$0 to$1K,Provid
35、es most services software designerneeds,Simple serial link is all that is requiredGood choice for code development whenhardware is stable,Can easily be integrated into a design teamenvironment,Debug Monitor:Disadvantages,Depends upon a stable memory subsystem in target,Not suitable for initial hw/sw
36、 integration,Not“real time”,System performance may differ with a debugger presentDebugger can co-exist with real time interrupts throughcareful assignment of interrupt priority levelsDifficulty in running out of ROM-based memory,Cant single step or insert breakpoints,Requires that the target has add
37、itional servicesFor many target systems this is an unacceptable costDebugger may not always have control of the system,Depends upon code being“well behaved”,ROM Emulator,Devices that plug into a ROM socket on targetsystem,but contain RAM rather than ROMComponents:,Cabling device to match mechanical
38、footprint of targetsystem ROM deviceFast RAM,Local control processor,Communication port to host,Additional features,such as trace memory,Provides a simple and fast way to download ROM-based code into a target system via the ROMsocket,Enables communications to host debugger fortarget systems that lac
39、k a serial port,ROM Emulator(Contd.)LAN,serial or parallelSimple plug-in probe substitutes for system ROMs,Main chassis-Overlay memory-Trace Capability-System control and host interface,Target system,ROM Emulator:Advantages,Very cost-effective($1K-$5K),Compatible with different memory configurations
40、High-speed download to target of large blocks ofcode,Can trace ROM code activity in real time,Can be integrated with other hw/sw integration toolsCan set breakpoints in“ROM”,Normally cannot do this in most target systems,ROM Emulator:Disadvantages,Requires target system memory to be in stableconditi
41、on,Only works if code is contained in standard ROM,Special ASIC,Microcontrollers with onboard ROM(e.g.8751),Real time trace is possible only if program executesdirectly out of ROM memory,Many targets transfer code to RAM for performancereasons,Hardware-assisted debug,Real time debugging places speci
42、al requirements ontools designed to control and observe the behaviorof embedded systems,Software debug monitors are ineffective when theprocessor-to-memory interface is not functional,Can be destroyed by code running wild,Transitory real time events cannot be observed,Debug monitor can perturb the t
43、arget system and mayinterfere or prevent its operation,Specialized tools have evolved to address the needsof real time system debugging,Oscilloscope,Used to examine any electrical signal,analog or digital,on any piece of hardware,Example:voltage on a pin,Restricted to about four inputsNo triggering
44、logic,Logic analyzer,A logic analyzer is an array of low-gradeoscilloscopes:,Logic Analyzer(Contd.),Checks whether electrical signal is at 1 or 0Multiple inputs,Can display data in two modes:,State:Data capture synchronous to processor clkTiming:Data capture synchronous to LA clk,Triggering logic:,D
45、isplay the values of input signals 1 through 4 onlywhen inputs 5 and 6 are both zero,Example:Tracking bus activityRecord state of the processor busses each clock cyclePost-processing software reduces trace to instructions,Memory Read Cycle,Memory Write Cycle,T1,T2,T3,T1,T2,T3,CLKADDRESS A0.AN,MREQRD
46、DATA D0.DNWRWAIT,Address Valid,DataValid,Address ValidDataValid,Logic Analyzer:Advantages,Most prevalent tool used for digital system designVery powerful measurement&triggeringcapabilities,Generic,easily customized with per-processormodule,Totally configurable to any currentmicroprocessor,200 channe
47、ls,1GHz data rates,Can observe entire digital system at the sametime,Can be used in conjunction with instrumentedcode for real time measurements in cachedprocessors,Logic Analyzer:Disadvantages,Can be very expensive,Strictly passive,cannot provide control ofprocessorComplex,Not well-integrated into
48、software designenvironment,Must combine with other tools for completesolution,Cached processors cannot be observed,Code must be instrumented if cache is not visible,In-circuit emulators(ICE),An ICE provides an integration of the mostimportant functions required to debugembedded systems,Microprocesso
49、r run Control(Debug monitor)Memory substitution(ROM Emulator)Real Time Trace(Logic Analyzer),A microprocessor in-circuit emulator is aspecially-instrumented microprocessor.,ngin,r,A typical engineer with emulatorEmulatorHost Computer,Typi,cal e,ee,Target system,ICE(Contd.),Host computer runs emulato
50、r control software,-Provides run control,-Displays real time trace at source level-Loads overlay memory with object code-High-speed link to emulation chassis,Probe head contain emulation microprocessor-Substitutes for,or disables target microprocessor-Contains run control circuitry and cable buffers
