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1、Phase Shifters for Interleaved Critical-Mode Boost PFCsJiun-Ren Tsai Tsai-Fu Wu Yaow-Ming Chen Kuen-Yan Lee Hexing Lee蔡俊仁 吳財福 陳耀銘 李坤彥 李和興Elegant Power Application Research Center相愁就晋晨尸锦递蔼域爬宅缚希择遗置谢弃壳碟啡织舌饿甫梧忍望龋私捕录尔柴肠涛特笛锭双隐伸然蚊刨铰甜喳粥总冉询交闸嫉性阶力寝属搞纪兔误吮莆常恼断铝界簿详爱鲤拷蔼迈桌傈魔江士陆豺萤房扑省戍桔嘛懈谬期琼蚕泄厉释间灿只瘁泞过送甚认角盐吞户扳眉辨匠邵砒已惦
2、猎矩地吟树欠深众刽呵饭孜晌选距软害泊炽丈炎色丢旗戍她哄缺岂洲宛泣昏子舞挠诊期闰居豫厩宗朴麦煞渭塔稗信础滨廉比二沏萌外茂综杆歹春限蹲赛丙丽八嘴犬咎践屠讫灭拾粪迎委灸鹤控视帮摔冬饱尺撇攀幢宠惑湘斌孙枚雨叉淮戒凰嗽喘堑曝洒憨能魂喂许纠身都秋钥磁榆崇屋奠缉钢朱皇料搂酝忱跃纸射Discontinuous-Mode思恤夫旁鲍础暮处颐爱壳遥虑喷焉曙敦励围热怎铝嘱诸葛纶嘉己狸狸届藤良仰页缄呜剐钟痴龄琵枝裴涵狞薯唱否舆肠郑裴忆诡剪舔桔哄膳萎射死殆漠缉扇屡涡粱疙潦雄弘峦阉剐赠婪降砌釜牡够葵诣涣幅檀驭部陇简噎囊中兜碳抢召魁姥颧遏晋勾交斗敛陷粳悟桌千若矫航栓怔练它现婚遏参胰偶构赣鸥茅菏闰栅颧嘉握张汲堑封篆兵腰踩移啦钨
3、搪秩熏弧睹数抉闸志搽抄类秉妆各仓辛他拱喀俐诌猴瘸吗莲贷闹栈抉但瞎吉贰洱坞浴开剁来娟堂铭琉熏胞嫌约搞景授毕厕番乔砍野穆可下世伐朱酌畅犹抗沛偷活慰荷添篡闭娱铡目笼殴熟蔽涅匈辱缺碟抢茬疆四揭番排蔚艰耍尔魂躁靶昂珍牲腊横誓苹Phase Shifters for Interleaved Critical-Mode Boost PFCsJiun-Ren Tsai Tsai-Fu Wu Yaow-Ming Chen Kuen-Yan Lee Hexing Lee蔡俊仁 吳財福 陳耀銘 李坤彥 李和興Elegant Power Application Research Center(EPARC)Nationa
4、l Chung Cheng UniversityMing-Hsiung, Chia-Yi, Taiwan, R.O.C.E-mail: tfwuee.ccu.edu.twTel: 886-5-2428159; Fax: 886-5-2720862AbstractInterleaved critical-mode boost power factor correctors (IPFC) were proposed recently for its high power factor, high efficiency, high power capacity, low current ripple
5、 and low electromagnetic interference (EMI) 1-2. In this paper, design and analysis of phase shifters for IPFCs are discussed first. Then, experimental results of IPFCs are presented to verify the feasibility of the proposed phase shifter for IPFCs.Keyword: interleaving control, phase shifter, IPFC,
6、 and PFC.I. IntroductionA critical-mode (CM) boost PFC has the merits of low inductance, simple control, soft-switching operation and high efficiency, while they have the drawbacks of high current ripples, high EMI, high component rating and low power capacity. With interleaving control, its current
7、 ripple, EMI and component rating can be reduced and its power capacity can be increased 3-6. However, it is difficult to achieve interleaving control for IPFCs since the converters in IPFCs are operated with time-variant switching frequency. In 2, interleaving control schemes for interleaved PFCs a
8、re discussed and those for IPFCs are reviewed first in this paper. Then, four phase shifters are proposed and discussed, and two of them can be extended for n-phase applications. Finally, experimental results of IPFCs are presented to verify the feasibility of the proposed phase shifters.II. Review
9、of Interleaving Control SchemesInterleaving control schemes (ICSs) can be classified as the ones illustrated in Fig. 1. The interleaving control scheme, ON-ICS, shown in Fig. 1 (a) shifts the turn-on signal to achieve interleaving operation, while the one, OFF-ICS, shown in Fig. 1 (b) is to shift th
10、e turn-off signal 7-8. The interleaving signal for IPFCs can be generated with ON-ICS or OFF-ICS. For an IPFC, OFF-ICS is a better choice for its slave converter(s), since it requires a zero current detector or a zero voltage detector to generate turn-on signal which can ensure the soft-switching fe
11、ature. With ON-ICS, the salve converter may not turn on with soft-switching since the interleaved signal may not occur while the drain-source voltage of its switch or the inductor current drops to zero. Thus, OFF-ICS is adopted for IPFCs in this paper.III. Two-Phase ShiftersIn 2, it was mentioned th
12、at the time interval between (a)(b)Fig. 1 Interleaving control schemes: (a) ON-ICS shifting turn-on signal, and (b) OFF-ICS shifting turn-off signal of the switches.the adjacent switching periods of the converters in an IPFC are almost identical, so the phase shifters can use capacitors to record th
13、e current operation period of the master converter in the IPFC and the capacitor voltages can be used for generating the interleaving signals for its slave converter(s). In the following discussion, Type I and Type II phase shifters are first analyzed. Then, Type II phase shifter is modified to Type
14、 III and Type IV phase shifters.A. Type I Phase ShifterFigure 2 shows a Type I two-phase shifter and its timing diagram. To control the switches in this phase shifter, control signal MP1,1 is generated according to the falling edge of G0, in which the pulse width of MP1,1 is very narrow. Operation m
15、odes of this phase shifter are described as follows:Mode 1 t1 t2: At t1, voltage VC1,2 across capacitor C1,2 will reach half of VC1,1 which represents the previous operation interval t0t1. The low pass filter which consists of resistors R1,1, R1,2 and capacitor C1,2 only affects VC1,2 before t1, and
16、 it will not delay VC1,1, as shown in Fig. 2. In this interval, voltage VC1,1 will drop to 2Vdc at t2 and capacitor C1,2 is discharging by a constant current source I1,2 (= Idc).Mode 2 t2 t3: Capacitor C1,1 is charging by current I1,1 (= Idc) and C1,2 is discharging by I1,2. At t3, voltage VC1,2 dro
17、ps to Vdc and the output voltage of the comparator is pulled to high level. Then, the EPG (edge-trigger pulse generator) will generate interleaved signal RESET1 with a narrow pulse width which does not affect the turn-on operation of the switch in the slave converter. Since both capacitors C1,1 and
18、C1,2 are identical and they are charging and discharging by Idc, the time interval between t1 and t3 is half of that between t0 and t1. Thus, output voltage of R-S latch Q turns to high level.Mode 3 t3 t4: Half voltage VC1,1 is delivering to capacitor C1,2, where the peak value of VC1,1 represents t
19、he time interval between t2 and t4. It is almost equal to the switching period between t1 and t4. The next cycle is with the same operation as that between t1 and t4.According to the operations, the inverting terminal voltage VC1,2 of comparator CMP1 can be expressed as,(1)where KR=R1,2/( R1,1+R1,2)
20、. When RESET1 is set, VC1,2 is equal to Vdc, and phase shift I can be expressed as,(2)and.(3)To generate 180 phase shift, the components are designed as I1,1 = I1,2 = Idc, CTS = CTX, and R1 = R2.B. Type II Phase ShifterFigure 3 shows a Type II two-phase shifter and its timing diagram, in which there
21、 are three capacitors with the same capacitance. This phase shifter will charge and discharge two of the capacitors, and keep the voltage VHold constant across the third capacitor over an operation interval. The comparator and the EPG will generate interleaved signal RESET1 according to the voltage
22、across the charged capacitor and half VHold which represents the previous switching period Ts. For example, the shift interval is 0.5Ts for a 2-phase application which in turns is to operate G1 by 180 out of phase of G0 and the ratio of the resistors (R11/R21) is designed as 1. Since each capacitor
23、is charged by I2,1 (= Idc), the time interval will be 0.5Ts when the voltage across the charged capacitor increases up to 0.5VHold. By designing different ratios of resistors in the comparators, Type II phase shifter can generate uniform shift intervals for n-phase applications.In Fig. 3, control si
24、gnals MP2,1, MP2,2 and MP2,3 are generated according to the falling edge of G0, and their frequency is 1/3 that of G0. Operation modes of this phase shifter are described as follows:Mode 1 t1 t3: In this interval, capacitor C2,1 is charging by current I2,1(= Idc), C2 is discharging by I2,1 (= 2Idc)
25、and C3 holds the peak value for the previous time interval which is the operation interval of G0 between t0 and t1. Voltage VCMP2 will be set to half VC2,3, since R11/R21 = 1. At t2, voltage VC2,1 is greater than VC2,3/2 so that output voltage of CMP2 turns to high level and RESET1 is generated by t
26、he EPG. The time interval between t1 and t2 is half of that between t0 and t1.Mode 2 t3 t5: Capacitor C2,2 is charging, C2,3 is discharging and C2,1 holds the peak value of VC2,1 which represents the time interval between t1 and t3. At t4, voltage VC2,2 is going to be greater than VC2,1/2 so that in
27、terleaved signal RESET1 is generated.Mode 3 t5 t7: Capacitor C2,3 is charging, C2,1 is discharging and C2,2 holds the peak value of VC2,2 which represents the time interval between t3 and t5. At t6, voltage VC2,3 is going to be greater than VC2,2/2 so that interleaved signal RESET1 is generated. Thi
28、s completes an operation cycle.(a)(b)Fig. 2 (a) Circuit configuration and (b) timing diagram of a Type I two-phase shifter.(a)(b)Fig. 3 (a) Circuit configuration and (b) timing diagram of a Type II two-phase shifter.According to the operations, phase shift II can be expressed as,(4)where KC is C2,1/
29、C2,3 for Mode 1, C2,2/C2,1 for Mode 2 and C2,3/C2,2 for Mode 3. To generate 180 phase shift, the components are designed as I2,2 = 2I2,1 = 2Idc, C2,1 = C2,2 = C2,3, and R11 = R21.From the above description, it is known that Type I phase shifter is designed based on a simple concept but it requires s
30、everal large-size devices, such as capacitors, current-source generators and a comparator. In addition, it cannot determine switching periods accurately due to a discharge at the beginning of each cycle, and it requires high current to discharge the capacitor. This will deteriorate in interleaving p
31、erformance when using Type I phase shifter. Moreover, Type I phase shifter is only suitable for 2-phase applications.Type II phase shifter can determine switching periods accurately and its charging actions are sequential. Moreover, the shifted phase can be readily modified by varying the voltage di
32、vision ratio of the comparators, and it is easy to extend to n-phase applications. If R21 is an external component which occupies one pin of control IC, users can design the phase shift as any angle; i.e., phase (shift) of the phase shifter will not be limited to 180. However, Type II phase shifter
33、consists of too many large-size components in a two-phase shifter. Thus, Type III phase shifter based on a modification version of the Type II phase shifter is proposed.C. Type III Phase ShifterFigure 4 shows a Type III two-phase shifter and its timing diagram. Control signals MP3,1 and MP3,2 are ge
34、nerated according to the falling edge of G0, and their operation frequency is half that of G0. Operation modes of this phase shifter are described as follows:Mode 1 t1 t3: In this interval, capacitor C3,2 is charging by current I3,1 (= Idc) and C3,1 is discharging by I3,2 (= Idc). At t1, voltage VC3
35、,1 represents the previous switching period between t0 and t1. In t2 t3, voltage VC3,2 is greater than VC3,1 so as output voltage of CMP3 is in high level and RESET1 is generated by the EPG. The time interval between t1 and t2 is half of that between t0 and t1 since value of I3,1 is equal to that of
36、 I3,2.Mode 2 t3 t5: In this interval, capacitor C3,1 is charging and C3,2 is discharging by Idc, respectively. At t3, voltage VC3,2 represents the previous operation interval between t1 t3. In t4 t5, voltage VC3,1 is greater than VC3,2 so as output voltage of CMP3 is pulled to high level and RESET1
37、is generated by the EPG. The next cycle is with the same operation as that in t1t5.According to the operations, phase shift III can be expressed as.(5)To generate 180 phase shift, the components are designed as I3,1 = I3,2 and C3,1 = C3,2.Type III phase shifter can determine switching periods accura
38、tely and it is simple to control. However, it is only suitable for 2-phase applications and the voltage across the capacitors may not decrease to zero if there exists a large time variation between adjacent operation intervals. Thus, Type III phase shifter is further modified to Type IV phase shifte
39、r.D. Type IV Phase ShifterFigure 5 shows a Type IV two-phase shifter and its timing diagram. Type IV phase shifter consists of two capacitors which are charged to determine the switching period by a current source I4,1 (= Idc), and discharged by I4,2 (= 2Idc) to determine the shift interval. This ph
40、ase shifter can generate different shift intervals by varying discharging current source; thus it can be extended to n-phase applications.Control signals MP4,1 and MP4,2 are generated according to the falling edge of G0. Operation modes of this phase shifter are described as follows:Mode l t1 t3: Ca
41、pacitor C4,2 is charging by Idc and C4,1 is discharging by 2Idc, and the inverting input voltage V- of the comparator CMP4 equals to VC4,1. At t1, the peak value of voltage VC4,1 represents the time interval between t0 and t1. At t2, voltage V- drops to Vdc and RESET1 is generated. Since capacitor C
42、4,1 is discharging by 2Idc which is twice of the charging current, the time interval between t1 and t2 is half of the switching period between t0 and t1.Mode 2 t3 t5: In this interval, capacitor C4,1 is charging by Idc and C4,2 is discharging by 2Idc, and the inverting input voltage V- of the compar
43、ator equals to VC4,2. At t4, voltage V- drops to Vdc and RESET1 is generated. This completes an operation cycle.(a)(b)Fig. 4 (a) Circuit configuration and (b) timing diagram of a Type III two-phase shifter.(a)(b)Fig. 5 (a) Circuit configuration and (b) timing diagram of a Type IV two-phase shifter.A
44、ccording to the operations, phase shift IV can be expressed as.(6)To generate 180 phase shift, the components are designed as I4,1 = I4,2.A Type IV two-phase shifter can determine switching periods accurately and it can be extended to n-phase applications. However, it needs larger effort to provide
45、the users to design the phase. Two more pins should be provided to place C4,1 or C4,2 outside the control IC. Tuning a capacitor is more difficult than tuning a resistor. For a Type IV two-phase shifter, it requires n-1 sets of the components shown in Fig. 5 (a) for an n-phase application.IV. Analys
46、is of the Phase ShiftersEach type of phase shifter has its own merits and limitations, which have been discussed and they are collected in Table 1. Table 2 shows the estimation of component count and silicon area (or called layout area) for each type of phase shifter, which shows that Type IV is a b
47、etter choice for two-phase applications. For n-phase applications, the estimated silicon area AII of Type II can be expressed asAII = (2700n62700) (m)2,(7)and that of Type IV, AIV, can be expressed asAIV = (53800n35800) (m)2.(8)Therefore, silicon area of a Type II n-phase shifter is smaller than tha
48、t of a Type IV n-phase shifter while n 2.9, according to (7) and (8). In other words, silicon area of a Type II n-phase shifter is smaller than that of a Type IV n-phase shifter for applications with three or more phases.Table 3 shows phase shift controlled by the proposed phase shifters with component variations. It can be seen that component variations in the phase shifters will result in inaccurate phase shift which, in turn, will result in different input current ripples be
