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1、AT89C51的介绍描述：AT89C51是一个低电压，高性能CMOS8位单片机带有4K字节的可反复擦写的程序存储器（PENROM）。和128字节的存取数据存储器（RAM），这种器件采用ATMEL公司的高密度、不容易丢失存储技术生产，并且能够与MCS-51系列的单片机兼容。片内含有8位中央处理器和闪烁存储单元，功能强大AT89C51单片机可为您提供许多高性价比的应用场合，可灵活应用于各种控制领域。主要性能参数：与MCS-51产品指令系统完全兼容4K字节可重擦写Flash闪速存储器1000次擦写周期数据保留时间：10年全静态操作：0Hz24MHz三级加密程序存储器1288字节内部RAM32个可编程
2、I/O口线2个16位定时/计数器6个中断源可编程串行UART通道低功耗空闲和掉电模式片内振荡器和时钟电路全双工UART串行中断口线双数据寄存器指针功能特性概述：AT89C51提供以下标准功能：4K字节Flash闪速存储器，128字节内部RAM，32个I/O口线，两个16位定时/计数器，一个5向量两级中断结构，一个全双工串行通信口，片内振荡器及时钟电路。同时，AT89C51可降至0Hz的静态逻辑操作，并支持两种软件可选的节电工作模式。空闲方式停止CPU的工作，但允许RAM，定时/计数器。串行通信口及中断系统继续工作。掉电方式保存RAM中的内容，但振荡器停止工作并禁止其它所有部件工作直到下一个硬件
3、复位。AT89C51单片机是一个行业标准架构，被广泛接受和应用，并作为一种开发工具。有许多工业供应商，他们供应这种控制器或把这种控制器集成到某种类型的系统芯片的结构。医学研究理事会和高级微电子研究所都选择这个设备，但他们论证的是两种截然不同固化工艺。医学研究理事会的实例是使用时间锁存，需要具体时间以确保单粒子效应减少到最低限度。高级微电子研究所采用超低功耗，以及布局和建筑固化工艺的设计原则来实现其结果。这些是与Aeroflex联合技术微电子中心（ UTMC ）完全不同的方法 ，抗辐射固化的AT89C51的工业供应商，利用抗辐射固化进程研制自己的AT89C51单片机。引脚功能说明：VCC：电源电
4、压GND：地P0口：P0口是一组8位漏极开路型双向I/O口，也即地址/数据总线复用口。作为输出口用时，每位能吸收电流的方式驱动8个TTL逻辑门电路，对端口写“1”可作为高阻抗输入端用。在访问外部数据存储器或程序存储器时，这组口线分时转换地址（低8位）和数据总线复用，在访问期间即或内部上拉电阻。在Flash编程时，P0口接收指令字节，而在程序校验时，输出指令字节，校验时，要求外接上拉电阻。P1口：P1是一个带有内部上拉电阻的8位双向I/O口，P1的输出缓冲级可驱动（吸收或输出电流）4个TTL逻辑门电路。对端口写“1”，通过内部的上拉电阻把端口拉到高电平，此时可作输入口。作输入口使用时，因为内部存
5、在上拉电阻，某个引脚被外部信号拉低时会输出一个电流（IIL）。Flash编程和程序校验期间，P1接收低8位地址。P2口：P2是一个带有内部上拉电阻的8位双向I/O口，P2的输出缓冲级可驱动（吸收或输出电流）4个TTL逻辑门电路。对端口写“1”，通过内部的上拉电阻把端口拉到高电平，此时可作输入口。作输入口使用时，因为内部存在上拉电阻，某个引脚被外部信号拉低时会输出一个电流（IIL）。在访问外部程序存储器或16位地址的外部数据存储器（例如执行MOVXDPTR指令）时，P2口送出高8位地址数据。在访问8位地址的外部数据存储器（如执行MOVXRI指令）时，P2口线上的内容在整个访问期间不改变。Flas
6、h编程或检验时，P2亦接收高位地址和其它控制信号。P3口：P3口是一组带有内部电阻的8位双向I/O口，P3口输出缓冲故可驱动4个TTL电路。当P3口写入“1”后，它们被内部上拉为高电平，并用作输入。作为输入，由于外部下拉为低电平，P3口将输出电流（ILL）这是由于上拉的缘故。P3口除了作为一般的I/O口外，更重要的用途是它的第二功能，如表1所示：表1 P3口第二功能端口引脚第二功能P3.0RXDP3.1TXDP3.2INT0P3.3INT1P3.4T0P3.5T1P3.6WRP3.7RDP3口还接收一些用于闪烁存储器编程和程序校验的控制信号。RET：复位输入。当振荡器工作时，RET引脚出现两个
7、机器周期以上高电平将使单片机复位。ALE/：当访问外部程序存储器或数据存储器时，ALE（地址锁存允许）输出脉冲用于锁存地址的低8位字节。对Flash存储器编程期间，该引脚还用于输入编程脉冲（）。即使不访问外部存储器，ALE仍以时钟振荡频率的1/6输出固定的正脉冲信号，因此它可对外输出时钟或用于定时目的。要注意的是：每当访问外部数据存储器时将跳过一个ALE脉冲。如有必要，可通过对特殊功能寄存器（SFR）区中的8EH单元的D0位置位，可禁止ALE操作。该位置位后，只有一条MOVX和MOVC指令ALE才会被激活。此外，该引脚会被微弱拉高，单片机执行外部程序时，应设置ALE无效。：程序储存允许（）输出
8、是外部程序存储器的读选通信号，当AT89C51由外部程序存储器取指令（或数据）时，每个机器周期两次有效，即输出两个脉冲。在此期间，当访问外部数据存储器，这两次有效的信号不出现。/VPP：外部访问允许。欲使CPU仅访问外部程序存储器（地址为0000HFFFFH），端必须保持低电平（接地）。需注意的是：如果加密位LB1被编程，复位时内部会锁存EA端状态。如端为高电平（接VCC端），CPU则执行内部程序存储器中的指令。当保持低电平时，则在此期间外部程序存储器（0000H-FFFFH），不管是否有内部程序存储器。Flash存储器编程时，该引脚加上+12V的编程允许电源VPP，当然这必须是该器件是使用1
9、2V编程电压VPP。XTAL1：振荡器反相放大器及内部时钟发生器的输入端。XTAL2：振荡器反相放大器的输出端。Ready/：字节编程的进度可通过RDY/输出信号监测，编程期间，ALE变为高电平“H”后P3.4（RDY/）端电平被拉低，表示正在编程状态（忙状态）。编程完成后，P3.4变为高电平表示准备就绪状态。振荡器特性：XTAL1和XTAL2分别为反向放大器的输入和输出。该反向放大器可以配置为片内振荡器。石晶振荡和陶瓷振荡均可采用。如采用外部时钟源驱动器件，XTAL2应不接。有余输入至内部时钟信号要通过一个二分频触发器，因此对外部时钟信号的脉宽无任何要求，但必须保证脉冲的高低电平要求的宽度。
10、时钟振荡器：AT89C51中有一个用于构成内部振荡器的高增益反相放大器，引脚XTAL1和XTAL2分别是该放大器的输入端和输出端。这个放大器与作为反馈元件的片外石英晶体 或陶瓷谐振器一起构成自激振荡器。用户也可以采用外部时钟。这种情况下，外部时钟脉冲接到XTAL1端，即内部时钟发生器的输入端，XTAL2则悬空。由于外部时钟信号是通过一个2分频触发器后作为内部时钟信号的，所以对外部时钟信号的占空比没有特殊要求，但最小高电平持续时间和最大的低电平持续时间应符合产品技术条件的要求。空闲节电模式：在空闲工作模式状态，CPU保持睡眠状态而所有片内的外设仍保持激活状态，这种方式由软件产生。此时，片内RAM
11、和所有特殊功能寄存器的内容保持不变。空闲模式可由任何允许的中断请求或硬件复位终止。通过硬件复位也可将空闲工作模式终止。需要注意的是：当由硬件复位来终止空闲工作模式时，CPU通常是从激活空闲模式那条指令的下一条指令开始继续执行程序的，要完成内部复位操作，硬件复位脉冲要保持两个机器周期有效，在这种情况下，内部禁止CPU访问片内RAM，而允许访问其它端口。为了避免可能对端口产生意外写入，激活空闲模式的那条指令后一条指令不应是一条对端口或外部存储器的写入指令。掉电模式：在掉电模式下，振荡器停止工作，进入掉电模式的指令是最后一条被执行的指令，片内RAM和特殊功能寄存器的内容在终止掉电模式前被冻结。退出掉
12、电模式的唯一方法是硬件复位，复位后将重新定义全部特殊功能寄存器但不改变RAM中的内容，在VCC恢复到正常工作电平前，复位应无效，且必须保持一定时间以使振荡器重启动并稳定工作。Flash闪速存储器的编程：AT89C51单片机内部有4K字节的Flash PEROM，这个Flash存储阵列出厂时已处于擦除状态（即所有存储单元的内容均为FFH），用户随时可对其进行编程。编程接口可接收高电压（+12V）或低电压（VCC）的允许编程信号。低电压编程模式适合于用户在线编程系统，而高电压编程模式可与通用EPROM编程器兼容。AT89C51的程序存储器阵列是采用字节写入方式编程的，每次写入一个字节，要对整个芯片
13、内的PEROM程序存储器写入一个非空字节，必须使用片擦除的方式将整个存储器的内容清除。编程方法：编程前，须根据表设置好地址、数据及控制信号。AT89C51编程方法如下：1、在地址线上加上要编程单元的地址信号。2、在数据线上加上要写入的数据字节。3、激活相应的控制信号。4、在高电压编程方式时，将EA/VPP端加上+12V编程电压。5、每对Flash存储阵列写入一个字节或每写入一个程序加密位，加上一个ALE/编程脉冲。改变编程单元的地址和写入的数据，重复15步骤，直到全部文件编程结束。每个字节写入周期是自身定时的，通常约为1.5ms。数据查询：AT89C51单片机用数据查询方式来检测一个写周期是否
14、结束，在一个写周期中，如需读取最后写入的那个字节，则读出的数据最高位是原来写入字节最高位的反码。写周期完成后，有效的数据就会出现在所有输出端上，此时，可进入下一个字节的写周期，写周期开始后，可在任意时刻进行数据查询。程序校验：如果加密位LB1、LB2没有进行编程，则代码数据可通过地址和数据线读回原编写的数据。加密位不可直接校验，加密位的校验可通过对存储器的校验和写入状态来验证。芯片擦除：整个PEROM阵列和三个锁定位的电擦除可通过正确的控制信号组合，并保持ALE管脚处于低电平10ms 来完成。在芯片擦操作中，代码阵列全被写“1”且在任何非空存储字节被重复编程以前，该操作必须被执行。 此外，AT
15、89C51设有稳态逻辑，可以在低到零频率的条件下静态逻辑，支持两种软件可选的掉电模式。在闲置模式下，CPU停止工作。但RAM，定时器，计数器，串口和中断系统仍在工作。在掉电模式下，保存RAM的内容并且冻结振荡器，禁止所用其他芯片功能，直到下一个硬件复位为止。读片内签名字节：读签名字节的过程和单元030H、031H及032H的正常校验相仿，只需将P3.6和P3.7保持低电平，返回值意义如下：(030H)=1EH声明产品由ATMEL公司制造(031H)=51H声明为AT89C51单片机(032H)=FFH声明为12V编程电压(032H)=05H声明为5V编程电压编程接口：采用控制信号的正确组合可对
16、Flash闪速存储阵列中的每一代码字节进行写入和存储器的整片擦除，写操作周期是自身定时的，初始化后它将自动定时到操作完成。看门狗（WDT）电路：看门狗（WDT）电路的主要是实现复位功能。当单片机运行出现死循环时,看门狗（WDT）电路可以起保护功能,实现复位作用。Introduction of AT89C51Description:The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash programmable and erasable read only memor
17、y (PEROM). The device is manufactured using Atmels high-density nonvolatile memory technology and is compatible with the industry-standard MCS-51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. B
18、y combining a versatile 8-bit CPU with Flash on a monolithic chip, the ATMEL Co.s AT89C51 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications.Features:Compatible with instruction set of MCS-51 products4K bytes of in-system re
19、programmable Flash memoryEndurance: 1000 write/erase cyclesData retention time: 10 yearsFully static operation: 0 Hz to 24 MHzThree-level program memory lock1288-bit internal RAM32 programmable I/O linesTwo 16-bit Timer/CountersSix interrupt sourceProgrammable serial channelLow-power idle and Power-
20、down modesOn-chip oscillator and clock circuitryFull-duplex UART serial port interrupt lineDual Data Pointer RegisterFunction Characteristic Description: The AT89C51 provides the following standard features: 4K bytes of Flash memory, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five
21、vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing
22、the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset. The 8051 microcontroller is an industry standard architecture that has broad acce
23、ptance, wide-ranging applications and development tools available. There are numerous commercial vendors that supply this controller or have it integrated into some type of system-on-a-chip structure. Both MRC and IAE chose this device to demonstrate two distinctly different technologies for hardeni
24、ng. The MRC example of this is to use temporal latches that require specific timing to ensure that single event effects are minimized. The IAE technology uses ultra low power, and layout and architecture HBD design rules to achieve their results. These are fundamentally different than the approach b
25、y Aeroflex-United Technologies Microelectronics Center (UTMC), the commercial vendor of a radiation hardened 8051, that built their 8051 microcontroller using radiation hardened processes. This broad range of technology within one device structure makes the 8051an ideal vehicle for performing this t
26、echnology evaluationPin Description:待添加的隐藏文字内容1VCC: Supply voltageGND: GroundPort 0: Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high impedance inputs. Port 0 may also be con
27、figured to be the multiplexed low order address/bus during accesses to external program and data memory. In this mode P0 has internal pull ups. Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pull ups are required during
28、program verification.Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pull ups and can be used as inputs. As inputs, Port 1 pins that are extern
29、ally being pulled low will source current (IIL) because of the internal pull ups.Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2: Port 2 is an 8-bit bi-directional I/O port with internal pull ups. The Port 2 output buffers can sink/source four TTL in
30、puts. When 1s are written to Port 2 pins they are pulled high by the internal pull ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull ups. Port 2 emits the high-order address byte during fetches from exter
31、nal program memory and during accesses to external data memory which uses 16-bit addresses (MOVX DPTR). In this application, it uses strong internal pull ups when emitting 1s. During accesses to external data memory which uses 8-bit addresses (MOVX RI). Port 2 emits the contents of the P2 Special Fu
32、nction Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3: Port 3 is an 8-bit bi-directional I/O port with internal pullups.The Port 3 output buffers can sink/source four TTL inputs. When the P3 I write 1 after, they a
33、re internal pull-up is high, and used as input. As input, due to the external pull-down for the low, P3 port output current (ILL) This is due to pull-ups sake. Port 3 also serves the functions of various special features of the AT89C51 as listed below: Port 3 also receives some control signals for F
34、lash programming and verification.RST: Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.ALE/: Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse inpu
35、t () during Flash programming. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory. If desired, ALE operation can be di
36、sabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.：Program Store Enable is the read strobe to ex
37、ternal program memory. When the AT89C51 is executing code from external program memory, is activated twice each machine cycle, except that two activations are skipped during each access to external data memory./ EA /VPP：External Access Enable. EA must be strapped to GND in order to enable the device
38、 to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. When / EA to maintain low, then during this period the external
39、program memory (0000H-FFFFH), regardless of whether an internal program memory. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming, for parts that require 12-volt VPP.XTAL1：Input to the inverting oscillator amplifier and input to the internal clock operating
40、 circuit.XTAL2：Output from the inverting oscillator amplifier.Ready/: The progress of byte programming can also be monitored by the RDY/output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY.Osci
41、llator Characteristics： XTAL1 and XTAL2 respectively, reverse amplifier input and output. The reverse amplifier can be configured as on-chip oscillator. Shi Jing oscillation and ceramic oscillation can be used. If using an external clock source drive the device, XTAL2 should not take. More than inpu
42、t to the internal clock signal through a two-way flip-flop, so the external clock signal pulse width without any request, but must ensure that the high-low pulse width requirements.Clock Oscillator： XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be config
43、ured for use as an on-chip oscillator. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven. There are no requirements on the duty cycle of the external clock signal, since the input to the
44、 internal clocking circuitry is through a divide by two flip trigger, but minimum and maximum voltage high and low time specifications must be observed.Idle Mode： In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software. The content
45、of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hardware reset, the device normally resumes program execution, from wher
46、e it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset,
47、 the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.Power-down Mode: In the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and special functio
48、n registers retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the special function registers but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.Programming the Flash: The AT89C51 is normally shipped with the on-chip Flash memory array in the erased
