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1、Memory 测试原理,Unit 1:Introduction to Flash Technology,Overview of Memory Devices,Nonvolatile,RAM,DRAM,SRAM,EEPROM,ROM,EPROM,PROM,Volatile,FLASH,Course Contents,Two Basic Memory Categories,Volatile Memory 易挥发存储器Data is lost when power is removed.Nonvolatile Memory非易挥发存储器Data remains even when power is
2、removed.,Volatile Memory,RAM Random Access MemorySRAM-Static RAM is commonly used as 640 Kb cache memory in computers.DRAM-Dynamic RAM is commonly used for read-write memory in computers.,Nonvolatile Memory,ROM Read Only Memory,ROM,are programmed in a wafer fab and cannot be erased or reprogrammed i
3、n the field.PROM Programmable ROM can be reprogrammed in the field by applying larger voltages with special equipment.EPROM Erasable PROM can be erased with UV light and reprogrammed with special equipment.EEPROM Electrically Erasable PROM can be erased with higher voltages and reprogrammed in the f
4、ield.,Nonvolatile Memory,NVRAM Nonvolatile RAM(Flash)is smaller than PROMs,less expensive,and easier to program and erase.Magnetic Magnetic disk and tape can be easily programmed and erased by user,but are slower than Flash.Optical CD ROM can be easily programmed by user but is slower than Flash.,Be
5、nefits of Flash Memory Chips,Smaller than EPROMS and EEPROMSRequires only one transistor and a storage capacitor per bit cell.Can be quickly and easily erased and reprogrammed without the need of special equipment.Excellent for use in cell phones,pagers,calculators,portable digital devices,automotiv
6、e,flight data recorders,and personal computers.,Simple ROM Memory Array,Simple DRAM Memory Array,Capacitorcharged,No current,“0”,Capacitoruncharged,Current flow,“1”,Activate Row to readIf capacitor was charged,no current flows on bit lineIf capacitor not charged,current flows on bit lineBuffer on co
7、lumn sense amps,Simple EPROM Memory Array,A second“floating gate”serves as the storage element in an EPROM.,Floating Gate,Source,Gate,Floating Gate(electrically isolated)is the storage element charged=“programmed”neutral=“erased”,Basic Flash Memory Cell,Flash Cell Structure-Similar to EPROM,except E
8、lectrically-erasable,p+Substrate,Control Gate,Floating Gate,Flash Cell Operation-Program Mode Channel Hot-Electron Injection,GND,VG=+9.3V,VD=+4.5V,Source,Drain,Flash Cell Operation-Program ModeChannel Hot-electron Injection,GND,VG=+9.3V,VD=+4.5V,Source,Drain,p+Substrate,Control Gate,Floating Gate,e-
9、,e-,e-,e-,e-,e-,e-,e-,e-,e-,e-,e-,e-,e-,Flash Cell Operation-Program ModeIDS Conduction&Floating Gate Charge(Q),p+Substrate,GND,VG=+9.3V,VD=+4.5V,Control Gate,Floating Gate,Source,Drain,Logic state“0”,Flash Cell Operation-Erase ModeNegative Gate-FN Tunneling,p+Substrate,Control Gate,e-,e-,e-,e-,e-,e
10、-,e-,e-,e-,e-,e-,e-,e-,e-,e-,Electrically-erasable charge from gate,Source,Drain,Logic state“1”,Flash Memory Bit Threshold Voltages,Flash Array Architecture(schematic),Core memory(core),Flash Array Cell Addressing,Row Decoder,Column Decoder,Source Switch,Basic Memory Device Internal Architecture,1,1
11、,1,1,0,0,0,0,0,0,0,0,0,0,0,0,A0,A1,A2,A3,A4,A5,A6,A7,Memory cell,Memory Cell block:每个CELL存储 data（1/0）Address Decoder Circuitry：地址译码 以(A0)来选择不同的memory cell or block进行读写操作。Input/Output I/O)circuitry：是memory Cell 和外界的输入输出接口，将data 在(D0)与Cell间传输。Control Circuitry：控制memory Cell 工作状态的电路 CE/OE/WE(Chip Enabl
12、e/Output Enable/Write Enable),Unit 2:Device Testing DC parametric testAC parametric testFunctional Test,DC parametric test,ISVM：Force current message voltageVSIM:Force voltage message current,DC Parametric Tests：测试 Address Decoder 和 I/O 回路 中Input/Output Buffer的DC特性。在DC Test中一般使用 VSIM 及ISVM 的方法。,DC C
13、ontact Check 开路/短路测试 OPEN/SHORTInput/Output Leakage Check 输入/输出漏电流测试 INLEAK/OUTLEAK CMOS Automatic Sleep CMOS自动睡眠模式电流测试 CMOSASM Standby Current Check Device不工作时待机电流测试 ICCSBOutput Drive Voltage&Current Device 电压及电流驱动能力测试 VOH/VOL,DC Parametric Test OPEN/SHOR TestINLEAK/OUTLEAK TestCMOSASMICCSB TestVOH
14、/VOL Test,Open Test,Purpose:测量 device pins 是否 correctly to DUT/Tester channel 测量 Device内部 管脚是否有开路。,Ground all pins(including VCC);Set Voltage Clamp 3.0 volts;Using PMU,force positive or negative current,one pin at a time;Measure resultant voltage;Fails test(open)if the absolute voltage measured is g
15、reater than 1.5V;,Test Method,Short Test,Purpose:测试 the device pins 是否有短路 Test Method:,Ground all pins(including VCC);Set Voltage Clamp 3.0 volts;Using PMU,force positive or negative Voltage,one pin at a time;Measure resultant current;Fails test(short)if the absolute voltage measured is less than 0.
16、2V.,Definition,IIL-Input leakage lowThe current in an input when it is forced low voltage.,IIH-Input leakage highThe current in an input when it is forced high voltage.,Why test?The IIL test measures the resistance from an input pin to VCC,IIH test measures the resistance from an input pin to VSS.Th
17、e test insures that the input buffers offer a high resistance when apply 0v and VCC.,Input Leakage Test(INLEAK),Input Leakage Low Test-IIL,Test Method,Apply VCCmax.Preconditioning all inputs to logic 1 with pin drivers.Input disable Using PMU,force individual inputs to VSS.Measure the current flows
18、from VCC to the pin being tested.Repeat the same test on each pin.Fails IIL if measured current is outside of the spec.,0V,Input Leakage High Test-IIH,Test Method,Apply VCCmax.Preconditioning all inputs to logic 0 with pin drivers.Input disable Using PMU,force individual inputs to VCC.Measure the cu
19、rrent flows from the pin being tested to VSS.Repeat the same test on each pin.Fails IIH if measured current is outside of the spec.,3.5V,Output Leakage Test-IOL,Purpose:To measure the output current leakage(1uA spec),Apply VCCmax.Preconditioning all Outputs to logic 1 with pin drivers.Output Disable
20、 Using PMU,force individual inputs to VCC.Measure the current flows from the pin being tested to VSS.Repeat the same test on each pin.Fails IOL if measured current is outside of the spec.,Test Method,Output Leakage Test-IOH,Purpose:To measure the output current leakage(1uA spec),Apply VCCmax.Precond
21、itioning all Outputs to logic 0 with pin drivers.Output Disable Using PMU,force individual inputs to VCC.Measure the current flows from the pin being tested to VSS.Repeat the same test on each pin.Fails IOH if measured current is outside of the spec.,Test Method,CMOSASM Test,Purpose:This test checks
22、 the CMOS Automatic Sleep Mode.It is a guardbanded tests using a Vcc which is 15-30%higher than Max.Vcc and tests against a limit of 10%guardband).The input pins are biased at the worst possible condition as well(lowest VIH and highest VIL).,Apply VCCmax.chip enabled,but at output disable state.(Aut
23、omatic Sleep Mode)Measure current flowing into VCC pin at VIH&VIL Failure CMOSASM when current is out of SPEC,Test Method,ICCSB Test,Purpose:This tests checks the Icc Standby Current(Icc3 in the TTL Table).This test should be done with all inputs high(VIH)and all inputs low(VIL).With the move to eli
24、minate the TTL table(most companies do NOT use TTL logic anymore),this test has decreasing importance.,Test Method,Apply VCCmax.chip disabled,but at output disable state.(Standby Mode)Measure current flowing into VCC pin at VIH&VIL Failure ICCSB when current is out of SPEC,Output voltages testing,VO
25、H/IOHVOL/IOL,Output voltages testing-VOH/IOH,Definition,VOH-represents the minimum voltage(V)produced by an output(O)when the output is in the logic 1(High)state.IOH-represents the current sourcing capabilities(I)of an output(O)when the output is in the logic 1(High)state.,Why test?VOH/IOH test meas
26、ures the resistance of an output pin when the output is in the logic 1 state.This test insures that the resistance of the output meets the design parameters and guarantees that the output will provide the specified IOH current while maintaining the proper VOH voltage.,Test Method,Apply VCCmin.Precon
27、dition output to logic 1(output high).Using PMU,force IOH current per specification.Wait 1 to 5 msec(Set PMU delay).Measure resultant voltage.Fails VOH of measured voltage is less than the limit.,Output voltages testing-VOH/IOH,Definition,VOL-represents the maximum voltage(V)produced by an output(O)
28、when the output is in the logic 0(Low)state.IOL-represents the current sinking capabilities(I)of an output(O)when the output is in the logic 0(Low)state.,Why test?VOL/IOL test measures the resistance of an output pin when the output is in the 0 state.This test insures that the resistance of the outp
29、ut meets the design parameters and guarantees that the output will provide the specified IOL current without exceeding the VOL voltage.,Output voltages testing-VOL/IOL,Test Method,DUT,Apply VCCmin.Precondition output to logic 0(output low).Using PMU,force IOL current per specification.Wait 1 to 5 ms
30、ec(Set PMU delay).Measure resultant voltage.Fails VOL of measured voltage is greater than the limit.,Output voltages testing,AC Parametric Testing,Output signal:-the rise&fall times.Relationship between input signals:-the setup&hold times.Relationship between input and output signals:-the delay time
31、s Successive relationship between input and output signals:-the speed test.,AC parametric test-Rise and Fall Time,Rise and Fall time-To guarantee that output data rise and fall rate.,AC parametric test-Setup Time TSD,Setup time-TSD to guarantee that input data can be read within a minimum amount of
32、time before a reference signal occurs.,AC parametric test-Hold Time THD,Hold time-THD to guarantee that input data can be read within a minimum amount of time after a reference signal occurs.,AC parametric test-Program Delay Time,Propagation Delay Measurements-TAA to guarantee that an output signal
33、can occur within a specified amount of time after the occurrence of a reference signal.,Functional Test,Functional Test：是为了保证Device的 工作是Match 它的Truth Table 而进行的测试。由Pattern Generator模拟正常的工作状态，输出Pattern 加入Device，将输出值与期望值相比较，Match 的为Pass，不Match 的为Fail。,Hierarchy in Reduced functional Faults,Stuck-At Fa
34、ultTransition FaultCoupling FaultNPSFNeighborhood Pattern Sensitive Fault,Stuck-At Fault,*The logic value of a stuck-at(SA)cell or line is always 0 or 1;it is always in state 0 or in state 1 and can not be changed to the opposite state.,Transition Fault,*A cell or line which fails to undergo a 0-1 t
35、ransition when it is written is said to contain an up transition fault;similarly,a down transition fault is the impossibility of making a 1-0 transition.,Coupling Fault,A write operation which generates an U or a Y transition in one cell changes the contents of a second cell,where U denotes a write
36、1 operation to a cell containing a 0 and Y denotes a write 0 operation to a cell containing a 1.The types of coupling faults used for DRAM are based on the following assumptions for read/write operations:A read operation will not cause an error.A non-transition write operation will not cause a fault
37、.A transition write operation may cause a fault.,Neighborhood Pattern Sensitive Fault,A Pattern Sensitive Fault(PSF)is defined as follows:The contents of a cell,or the ability to change the contents,is influenced by the contents of all other cells in the memory.The PSF can be considered the most gen
38、eral case of the k-coupling fault.The PSF model allows the neighborhood to take on any position in the memory array.When the neighborhood is allowed to take on only a single position,one speaks about a Neighborhood Pattern Sensitive Fault(NPSF).,Function Test Item Example,READ0/READALL+EMBERASE+BLAN
39、K PRGDIAG VERDIAG PRGRVCK RVCKSP PRGSP1/2 PRGCKBD,READ0/READALL+PREERASE+BLANK,These test blocks work together to insure the array is blank before testing continues.A portion of the array is read using READ0 or READALL(depending on the flow).Devices which fail this initial blank check are PREERASE,a
40、nd then the erase is verified with a full Blank Check.,Description:,PRGDIAG*,PRGDIAG Embedded Programs a reverse DIAG pattern.Each byte/word must program within SPECHot temperature is worst-case since column leakage is at its highest levels.Only the programmed 0s are verified at this test block.,Des
41、cription:,VERDIAG,Reads both 1s and 0s of the DIAG pattern.The DIAG pattern is designed to reveal metal shorts(M1-M1,M1-M2,and M2-M2)which cause blank bits to program adjacent to the target programming bit.Programming only one bit per column helps reveal this type of defect.In Figure,the array on th
42、e right has a metal short between columns(bitlines)2 and 3.The short accidentally shares the programming drain voltage between the two columns.The programming wordline voltage is common across a row,so programming any bit in column 2 accidentally programs the adjacent bit in column 3.,Description:,T
43、his is called bit pickup,PRGRVCK-Programming Reverse CKBD,Description:,RVCK is a worst-case pattern for speed since outputs switch on every address transition(1-0-1-0).,RVCKSP*-Reverse CKBD Speed,RVCKSP tests AC speed by reading the RVCK pattern with tight timing.There are usually six speed grades.T
44、he program tests units starting with the fastest speed bin,and moving through the six grades until finding a passing bin.The actual speed values of the six bins vary from program to program,depending on the speed distribution of the part and Marketing requirements.An example of 3V speed grades is sh
45、own below:,Description:,PRGSP1/2*-Program Speed,The PRGSP1/2 blocks test the AC write parameters It Embedded Programs one row and one column using tight timing parameters and address/data formatting.A programming failure indicates the write command was not accepted due to the tight write parameters.
46、,Description:,PRGCKBD*-Programming Checkerboard/Check board verify,Programs a CKBD pattern,which alternates 1s and 0s through the entire array.This checks the programmability of half the array.The surrounding blank bits are NOT read in this test,they are checked in Checkerboard Verify.,Programming C
47、heckerboard Description:,PRGCKBD*-Programming Checkerboard/Check board verify,Reads both 1s and 0s of the CKBD pattern.The CKBD pattern is designed to reveal bit-to-bit shorts,typically caused by poly 1 to poly 1 shorts.Unlike metal shorts which affect entire columns,the poly 1 shorts only affect bi
48、ts adjacent to the short.So every pair of bits must be checked.By alternating 1s and 0s through the whole array,the CKBD pattern accomplishes this task.,Checkerboard Verify Description:,Class Test Flow,Parametrics Opens,Shorts,Icc power tests,Input/Output Lkg,Class Test Flow(Continues),RVCKSP*AC spe
49、ed read of RVCK pattern,Basic Test System Components,Pattern Memory for Parallel and Scan Vectors,Timing Formatting,Masking and Timeset Memory,Special Tester Options,Network Interface,System Clocks and Calibration Circuits,CPU with Hard Disk,Tape Drive,Keyboard&Video,Internal Controller CPU,System Power Supplies,DPS and Reference Supplies(for VCC,VIL,VIH,VOL,VOH),PMU Precision Measurement Unit,Test Head Pin Electronics Drivers,Comparators,Current Loads,etc.,Load Board with DUT,The End,
