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1、大规模数字集成电路设计第二章VHDL语言程序的基本结构,本章要点,VHDL程序的宏观结构；实体的基本格式及其在VHDL硬件设计中的应用构造体的基本格式及其在VHDL硬件设计中的基本功能库的实用意义及使用方法。,2.1 VHDL程序组成部分及其功能,VHDL程序,实体（Entity）构造体（Architecture）配置（Configuration）包集合（Package）库（Library）,设计共享部分,需编写的部分,VHDL描述的总体结构,2.1 VHDL程序组成部分及其功能,VHDL程序,实体（Entity）构造体（Architecture）配置（Configuration）包集合（Pa
2、ckage）库（Library）,基本设计单元所必需的部分,实体-规定设计单元的输入输出接口信号和引脚构造体-定义设计单元的具体构造或功能（行为）,2.2 实体,实体说明的结构ENTITY 实体名 IS【类属参数说明】；【端口说明】；END 实体名；,2.2 实体说明,端口说明1）端口名2）端口方向3）数据类型,2.2 实体说明,端口说明 端口说明是对设计实体与外部接口的描述。包括对引脚信号名称、引脚信号的数据类型、以及信号的输入、输出方向的描述。PORT（端口名：；端口名：方向 数据类型）；,方向,数据类型,2.3 构造体,构造体的结构ARCHITECTURE 构造体名 OF 实体名 IS【
3、定义语句】内部信号、常数、数据类型等的定义；BEGIN【并行处理语句】；END 构造体名；,2.3 构造体,1）构造体的命名 2）定义语句 3）并行处理语句,2.3 构造体,一个完整的构造体由两个基本层次组成：,2)描述实体逻辑行为的，以各种不同的描述风格表示的功能描述语句。,1）对数据类型，常数，信号，子程序和元件等元素的说明部分。,【例1】二选一选择器,AND,NOT,AND,OR,D1,SEL,D0,Q,tmp1,tmp2,MUX2ID0,Entity mux2id0 isPort(d0,d1,sel:in bit;q:out bit);End mux2id0;Architecture
4、struc of mux isBeginprocess(d0,d1,sel)variable tmp1,tmp2,tmp3:bit;begintmp1:=d0 AND sel;tmp2:=d1 AND(NOT sel);q=tmp1 OR tmp2;end process;End struc;,【例1】二选一选择器,【例 1-2】二选一选择器的构造体说明(续),ARCHITECTURE connect OF mux IS-构造体定义BEGIN-构造体开始标记 PROCESS(d0,d1,sel)-进程 VARIABLE tmp1,tmp2,tmp3:BIT;-变量的声明 BEGIN-进程开始标
5、记 tmp1:=d0 AND sel;-变量赋值语句 tmp2:=d1 AND(NOT sel);-变量赋值语句 q=tmp1 OR tmp2;-信号赋值语句 END PROCESS;-进程结束END connect;-构造体结束,【例 1-2】二选一选择器的构造体说明(续),ARCHITECTURE connect OF mux IS-构造体定义BEGIN-构造体开始标记 PROCESS(d0,d1,sel)-进程1。END PROCESS;-进程1结束 PROCESS(d0,d1,sel)-进程2。END PROCESS;-进程2结束。-其它并行语句结构 END connect;-构造体结
6、束,Used to make associations within models Associate a Entity and Architecture Associate a component to an Entity-ArchitectureWidely used in Simulation environments Provides a flexible and fast path to design alternatives Limited or no support in Synthesis environmentsCONFIGURATION OF ISFOR END FOR;E
7、ND;(1076-1987 version)END CONFIGURATION;(1076-1993 version),2.4 配置（Configuration）,Putting it all together,Packages are a convenient way of storing and using information throughout an entire model.Packages consist of:Package Declaration(Required)Type declarationsSubprograms declarations Package Body(
8、Optional)Subprogram definitions VHDL has two built-in Packages Standard TEXTIO,2.4 包集合（Package）,2.5 库,Contains a package or a collection of packages.Resource Libraries Standard Package IEEE developed packages Altera Component packages Any library of design units that are referenced in a design.Worki
9、ng Library Library into which the unit is being compiled.必须放在VHDL程序最前面;在VHDL程序中，可以有多个库，库和库之间相互独立;,All packages must be compiled Implicit Libraries Work STD Note:Items in these packages do not need to be referenced,they are implied.LIBRARY Clause Defines the library name that can be referenced.Is a s
10、ymbolic name to path/directory.Defined by the Compiler Tool.USE Clause Specifies the package and object in the library that you have specified in the Library clause.,2.5 库,LIBRARY STD,Contains the following packages:standard(Types:Bit,Boolean,Integer,Real,and Time.All operator functions to support t
11、ypes)textio(File operations)An implicit library(built-in)Does not need to be referenced in VHDL design,Types defined in Standard Package,Type BIT 2 logic value system(0,1)signal a_temp:bit;BIT_VECTOR array of bitssignal temp:bit_vector(3 downto 0);signal temp:bit_vector(0 to 3);Type BOOLEAN(false,tr
12、ue)Integer Positive and negative values in decimalsignal int_tmp:integer;-32 bit numbersignal int_tmp1:integer range 0 to 255;-8 bit numberNote:Standard package has other types,2.4.1 库的种类,1）IEEE库std_logic_1164(std_logic types&related functions)std_logic_arith(arithmetic functions)std_logic_signed(si
13、gned arithmetic functions)std_logic_unsigned(unsigned arithmetic functions)2）STD库 standard(Types:Bit,Boolean,Integer,Real,and Time.All operator functions to support types)textio(File operations),LIBRARY IEEE,Contains the following packages:std_logic_1164(std_logic types&related functions)std_logic_a
14、rith(arithmetic functions)std_logic_signed(signed arithmetic functions)std_logic_unsigned(unsigned arithmetic functions),Types defined in std_logic_1164 Package,Type STD_LOGIC 9 logic value system(U,X,0,1,Z,W,L,H,-)W,L,H”weak values(Not supported by Synthesis)X-used for unknown Z-(not z)used for tri
15、-state-Dont Care Resolved type:supports,signals with multiple drives.Type STD_ULOGIC Same 9 value system as STD_LOGIC Unresolved type:Does not support multiple signal drives.Error will occur.,2.4.1 库的使用,1）库的声明LIBRARY library_name;USE library_name.package_name.ITEM.name;2）库的使用范围从一个实体说明开始到它所属的构造体、配置为止
16、。,【例2】二选一选择器,LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY mux ISGENERIC(m:TIME:=1ns);PORT(d0,d1:IN STD_LOGIC_VECTOR(7 DOWNTO 0);sel:IN STD_LOGIC;q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END mux;,Putting it all together,VHDL描述的总体结构,作 业,请写出带同步清零端clr的D触发器的实体部分。,IN输入OUT输出INOUT双向BUFFER输出，构造体内部可再使用LINKAGE不指定方向，无论哪个方向都可连接,标准数据类型,Package Example,
