《Lecture5简单数字电路设计-组合电路.ppt》由会员分享，可在线阅读，更多相关《Lecture5简单数字电路设计-组合电路.ppt（26页珍藏版）》请在三一办公上搜索。
1、Verilog HDL语言,华中科技大学计算机科学与技术学院,主讲：胡迪青Email:QQ:121374333,2,简单数字电路设计,3,设计验证与仿真,Verilog HDL不仅提供描述设计的能力，而且提供对激励、控制、存储响应和设计验证的建模能力。激励和控制可用初始化语句产生。验证运行过程中的响应可以作为“变化时保存”或作为选通的数据存储。最后，设计验证可以通过在初始化语句中写入相应的语句自动与期望的响应值比较完成。要测试一个设计块是否正确，就要用Verilog再写一个测试模块。这个测试模块应包括以下三个方面的内容：测试模块中要调用到设计块，只有这样才能对它进行测试；测试模块中应包含测试的
2、激励信号源；测试模块能够实施对输出信号的检测，并报告检测结果。,4,Simulating/Validating HDL,The sad truth10%design,90%validationIf you do it right you will spend 9X more time testing/validating a design than designing it.,5,Testbench Example(contrived but valid),module test_and;integer file,i,code;reg a,b,expect,clock;wire out;par
3、ameter cycle=20;and#4 a0(out,a,b);/Circuit under testinitial begin:file_block clock=0;file=$fopen(compare.txt,“r”);for(i=0;i 4;i=i+1)begin(posedge clock)/Read stimulus on rising clock code=$fscanf(file,%b%b%bn,a,b,expect);#(cycle-1)/Compare just before end of cycle if(expect!=out)$strobe(%d%b%b%b%b,
4、$time,a,b,expect,out);end/for$fclose(file);$stop;end/initialalways#(cycle/2)clock=clock;/Clock generatorendmodule,6,组合逻辑设计,组合逻辑电路 可以有若个输入变量和若干个输出变量，其每个输出变量是其输入的逻辑函数，其每个时刻的输出变量的状态仅与当时的输入变量的状态有关，与本输出的原来状态及输入的原状态无关，也就是输入状态的变化立即反映在输出状态的变化。逻辑电路的各种运算可以用布尔代数来描述狄摩根定律利用狄摩根（DeMorgan）定律可以将积之和形式的电路转换为和之积形式的电路，或
5、反之。,7,组合逻辑的三种通用表示方法结构化（即门级）原理图真值表布尔方程式实例：半加器,8,Combinational CircuitsComponent Instantiations,Circuit A connection of modules,Also known as structure A circuit is a second way to describe a,module,vs.using an always procedure,as earlier,Instance An occurrence of a module in acircuit May be multiple
6、instances of a module,e.g.,Cars modules:tires,engine,windows,etc.,with 4 tire instances,1 engine instance,6 window instances,etc.,9,Combinational CircuitsModule Instantiations,10,Combinational CircuitsModule Instantiations,11,Combinational CircuitsModule Instantiations,12,Combinational Circuit Struc
7、tureSimulatingg the Circuit,Same testbench format for BeltWarnmodule as for earlier And2 module,13,Combinational Circuit StructureSimulatingg the Circuit,14,Combinational Circuit StructureSimulatingg the Circuit,timescale 1 ns/1 nsmodule Testbench();reg K_s,P_s,S_s;wire W_s;BeltWarn CompToTest(K_s,P
8、_s,S_s,W_s);initial begin,More on testbenches Note that a single module instantiationstatement used reg and wire declarations(K_s,P_s,S_s,W_s)used because procedurecannot access instantiated modules,=0;S_sP_s=1;P_s=1;P_s=1;,=0;S_s=0;S_s=0;S_s=1;,K_s=0;P_s#10 K_s=0;#10 K_s=1;#10 K_s=1;endendmodule,po
9、rts directly Inputs declared as regs so can assignvalues(which are held betweenassignments)Note module instantiation statement,and procedure can both appear in onemodule,15,Combinational Behavior to Structure,16,Combinational Behavior to StructureAlways Procedures with Assignment Statements,17,Combi
10、national Behavior to StructureProcedures with Assignment Statements,Procedural assignment statement Assigns value to variable Right side may be expression ofoperators,timescale 1 ns/1 nsmodule BeltWarn(K,P,S,W);input K,P,S;output W;reg W;,Built-in bit operators include&AND|OR,NOT,XOR,XNOR,always(K,P
11、,S)beginW=K,end,endmodule Q:Create an always procedure tocompute:,F=CH+CHAnswer 1:always(C,H)beginF=(Cend,Answer 2:always(C,H)beginF=C H;,end,18,Combinational Behavior to StructureProcedures with Assignment Statements,Procedure may have multipleassignment statements,timescale 1 ns/1 nsmodule TwoOutp
12、utEx(A,B,C,F,G);,input A,B,C;output FF,G;reg F,G;always(A,B,C)beginF=(B endendmodule,19,Combinational Behavior to StructureProcedures with If-Else Statements,Process may use if-else statements(a.k.a.conditional statements),if(expression)If expression is true(evaluates tononzero value),executecorresp
13、onding statement(s)If false(evaluates to 0),executeelsess statement(else part isoptional)Example shows use of operator=,timescale 1 ns/1 nsmodule BeltWarn(K,P,S,W);input K,P,S;output W;reg W;always(K,P,S)beginif(K else,W=0;,logical equality,returns true/false(actually,returns 1 or 0),endendmodule,Tr
14、ue is nonzero value,false is zero,20,Combinational Behavior to StructureProcedures with If-Else Statements,More than two possibilities,Handled by stringing if-elsestatements together Known as if-else-if construct,Example:4x1 mux behavior,timescale 1 ns/1 nsmodule Mux4(I3,I2,I1,I0,S1,S0,D);input I3,I
15、2,I1,I0;,input S1,S0;output D;,SupposeS1S0change to01,Suppose S1S0 change to 01 ifs expression is false elses statement executes,which is an if statementwhose expression is true,reg D;always(I3,I2,I1,I0,S1,S0)beginif(S1=0,else if(S1=1,Note:The following indentation shows ifstatement nesting,but is u
16、nconventional:if(S1=0&S0=0),endendmodule,D=I0;else,if(S1=0 else,&,logical AND,&:bit AND(operands are bits,returns bit)&:logical AND(operands are true/false,if(S1=1,elseD=I3;,values,returns true/false),21,Combinational Behavior to StructureProcedures with If-Else Statements,22,Combinational Behavior
17、to Structure,23,Combinational Behavior to StructureCommon Pitfall Missing Inputs from Event Control Expression,24,Combinational Behavior to StructureCommon Pitfall Missing Inputs from Event Control Expression,Verilog provides mechanism to help avoidthis pitfall,*implicit event control expression Aut
18、omatically adds all nets and variablesthat are read by the controlled statement orstatement group Thus,*in example is equivalent to(S1,S0,I0,I1,I2,I3),timescale 1 ns/1 nsmodule Mux4(I3,I2,I1,I0,S1,S0,D);input I3,I2,I1,I0;input S1,S0;output D;reg D;,(*)also equivalentalways*beginif(S1=0 endendmodule,
19、25,Combinational Behavior to StructureCommon Pitfall Output not Assigned on Every Pass,26,Combinational Behavior to StructureCommon Pitfall Output not Assigned on Every Pass,Same pitfall often occurs due to not considering allpossible input combinationsif(I1=0 endelse if(I1=1&I0=0)begin,D3=0;D2=1;,D1=0;D0=0;,Last else missing,so not all,end,input combinations are covered(i.e.,I1I0=11 not covered),
