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1、ICT測試原理及程式簡介,EPDVIII ICTRandy .xiang,一.ICT的功能,ICT也叫在線測試儀，是一台靜態元件測試儀，它能准確，高速地測量PCB上已裝元件的不良問題，包括元件的漏件，錯件，裝反，空焊，來料不良，PCB上金道之間的開短路等。可測元件包括：電阻，電容，二極管，三極管，電感，變壓器，IC等絕大多數電子元件。,二. ICT的硬件結構,ICT包括ICT系統主機，電腦系統，壓床，測試治具。其中ICT系統主機包括：電源部分，量測控制板，I/O卡，DC量測板，AC量測板，開關板，HP-JET量測板，高壓量測板(選配件)。,公司: TRI (Test Research Inc.
2、)德律科技產地: 台灣,工作條件治具類型: 真空治具.真空壓力: 最小56cmHg.外部真空管2根.氣壓: 4kg/cm2 6kg/cm2.氣壓管1根.操作溫度: 0。C 30。C.環境濕度: 25% RH-75%RH.最小工作空間:深：1.5 公尺。寬：2.0 公尺。高：2.0 公尺。,TRI 8001測試畫面,公司: TRI (Test Research Inc.)德律科技產地: 台灣,工作條件電源:3 AC 220V-245V, 50/60 Hz5% 氣壓: 46KGFCM2,TRI 518測試操作畫面,相匹配的治具簡介,相匹配的治具必需為真空治具, 即治具下壓的動力為真空. 真空治具根
3、據繞線長度分為: 長線治具,短線治具和無線治具. 我們現在使用的治具為長線治具. 治具內部結構如下:,探針,彈簧,密封墊,Interface,Introduction of Agilent 3070,Agilent 3070 Family,307X, up to 5200 nodes,327X, up to 1300 nodes,317X, up to 2600 nodes,Anatomy of the Agilent Medalist 3070,Agilent 3070 Hardware,Agilent 3070,Electronics Cabinet,DUT power suppliesE
4、xternal Instruments,Test Fixture,Mother Board (one per bank),Module power Supplies,Agilent3070 測試畫面,Anatomy of the Agilent Medalist i3070 Fixture,Probe to Pin Wiring,Test Probe,Support Plate,Probe Plate,Personality Pin,Alignment Plate,Printed Circuit Board,Fixture Frame,Vacuum Gasket,R1,Anatomy of t
5、he Agilent Medalist 3070,Agilent 3070 TestHead,Bank 2 Bank 1,Module 2 Module 0Module 3 Module 1,Slot 1: ASRUSlot 6: Module Control CardAll others: Pin Cards,Pin 78 - 1,Pin 1 - 78,Fixture Numbering,Anatomy of the Agilent Medalist 3070 The Module Control Cards The Analog Stimulus - Response Unit (ASRU
6、),Agilent 3070 Module,Mother card,ASRU card,Control card,Pin card,Slot 1,Slot 2,Slot 3,Pin card,Slot 4,Slot 8,Slot 6,Slot 7,Slot 5,Slot 9,Slot 10,Slot 11,Pin card,Pin card,Pin card,Pin card,Pin card,Pin card,Pin card,Module card configuration,ASRU Card,提供模拟激励信号使用测量运算放大器进行反馈信号的测量 提供上电测试的电源通道配在每个模块第1号
7、插槽,Module Control Card,控制实际的测试过程 2个rcvc,测试频率带有8个通用开关 (GP Relay) 配在每个模块的第 6 号插槽,MUX,S I A B L G,MOA,Detector,Aux,Source,Hybrid Double Density,Channel A,Channel B. . . . . . . . . . . .,Channel H,Pin Card,X1.X8 XG XL,Analog Subsystem,Digital Subsystem,9:2,ASRU,Hybrid 32 Card,ICT TEST程式与夾具命名規則,1.ICT程式命
8、名規則 設備型號T(TR8001,TR518), A(Agilent 3070) T,A+ P/N+EC+ 夾具套數 2.ICT夾具命名規則 設備型號T,A+P/N+夾具套數,MHS机种为例：,P/N：69Y4784 EC:N31078RICT程式命名:A90Y4784N31078R_01ICT程式命名:A90Y4784_01,三. ICT的基本測試原理,1. 隔離量測原理 ICT其實是一台高級的萬用表，但它具有隔離(GUARDING)功能，這是它不同于萬用表的最大特點。GUARDING的作用是使一個被測元件在測試時不受旁路元件的影響，而萬用表做不到這一點。在 ICT 內部電路中利用一顆 OP
9、放大器 當做一個隔離點（最多可有五個隔離點），如果是:,source: http:/,An Overview of 3070 Test,Part 3,Pins Test,Pins测试概述,ICT测试的原理要求夹具的探针和电路板的测试点(testpad)要有良好的电气接触.Pins测试就是在测试正式开始前验证探针和测试点有无接触的工序.Pins测试只定性验证有无接触，pins pass是最低要求，并不能保证接触良好.(绕线出现错误；pins接触不好，阻抗大，但依然有current flow;隔离点无法 测),Pins Test,“A”,“B”,“C”,“D”,“E”,“F”,“G”,“Node_
10、Names”,S,Node E has no current flow. It is capacitively isolated and cannot be tested in Pins Test.,Pins Test - Syntax,nodes Anodes Bnodes Cnodes D!nodes E” ! node capacitively isolatednodes ”Fnodes ”G,Pins Test Called from testplan,Pins test的预定义 sub Set_Custom_Option global Off, Pretest, Failure ！设
11、置全局常量 global Chek_Point_Mode Chek_Point_Mode=Pretest !choose Off, Pretest, Failure ！选择pins测试模式，off不进行pins测试 ！pretest在其它测试前进行pins测试 ！failure其它测试fail后，进行pins测试end sub,Pins测试的调试,Pins测试中的节点排列顺序不影响测试结果Pins测试中没有其他测试选项所以pins测试只有node的取舍 哪些节点pins不可测?电容阻隔的点（capacitively isolated） IPG自动注释只连到IC的NC脚的 IPG自动注释所连器件
12、在板上都没有放(no pop)的 手动确认,Part 4,Shorts Test & Opens Test,Shorts Test overview,Shorts Test,! IPG: rev B.03.60 threshold 12settling delay 50.00usettling delay 525.0ushort “L201-1” to “L201-2”settling delay 50.00ushort “J201-1” to “J201-2”. . .threshold 1000. . .nodes “Data7”nodes “R201-2”nodes “R201-1”.
13、. .threshold 8. . .nodes “R202-2”nodes “R202-1”nodes “GND”,L201Series Resistance = 6ohms,R202 at 33ohms,R201 at 20k,R201-1,R201-2,R202-1,R202-2,Expected Shorts,如图，对L201 进行shorts测试，预期为短路。a).设置阀值为12欧姆，如果R测量12(threshold) ， 则测试pass，反之，fail。 b).设置从加信号到开始测量的延时，以致等待信号稳定。c).测量两个节点之间的阻值，并判断！语法如下：! In the “sh
14、orts” file ! Syntax ! short “Node_1” to “Node_2” !threshold 12Settling delay 50uSettling delay 525uShorts “L201-1” to “L201-2,Shorts Test (Good Board)Testing For Shorts,“A”,“B”,“C”,“D”,“E”,“F”,“G”,“Node_Names”,Shorts Test (Bad Board)Testing For Shorts,“A”,“B”,“C”,“D”,“E”,“F”,“G”,Shorts Test (Bad Boa
15、rd)Testing For Shorts,“A”,“B”,“C”,“D”,“E”,“F”,“G”,假象短路的调试,假象短路出现的原因是特定的节点的测试顺序造成误判,必须在程序发布前排除方法是将出错的节点（或者节点群）挪到被短路的节点(或节点群）后面。这个过程在调试中可能要重复几次,挪动时最好在同一个threshold设置群之内.可以自己设置threshold，但是要遵循threshold值从大到小的顺序, Threshold最低尽量不要设到4以下，尤其是电源点。否则会有漏掉真正短路的可能.不要轻易把节点放到测试文件的末尾，这样可能造成开短路 覆盖率的缺失，尤其是电源点或者VCC这类本身就是低
16、阻抗的节点.调试时settling delay可以加的比较大，在优化时再减小,Shorts Test - Report Options,report common devicesreport limit 12Short #1From: D3 22044To: D4 21938Common Devices: U1 U4,report netlist, common devicesreport limit 12Short #1From: D3 22044 u1.5 u4.3 u5.2 u7.5To: D4 21938 u1.8 u4.4 u6.2 u2.10 Common Devices: u1
17、u4,report phantomsShort #1From: D3 22044To: D4 21938,Part 5,Analog TestcapacitorsconnectorsdiodesFETsfusesinductorsjumpersresistorsswitchestransistorszeners,Part 6,Testjet & VTEP & iVTEP,The VTEP/iVTEP/TestJet Test,BGA with floating metal tops/heat spreaders are testable!,PCB,AC Signal,Ground,VTEP S
18、ensor plate,C measured,Electronics board(Amplifier),To MultiplexCard,Metal BGA Under-Test,FloatingMetal Top,TestJet测试能力的极限值为20fF，VTEP测试能力的极限值为5fF。低于5的值使用iVTEP来进行测试，但是iVTEP的测试速度比较慢，而且不能用来测试连接器。,Bar = Num Pins in Range,0,5,10,15,20,25,30,0 to 5,5 to 10,10 to 15,15 to 20,20 to 25,25 to 30,30 to 35,35 t
19、o 40,40 to 45,45 to 50,Measurement (in fF),TestJET和VTEP的测试界限,Aug, 2010,The VTEP/TestJet Verification,The TestJet Test,default threshold low 20 high 10000device “u1” test pins 1 test pins 2, 3 test pins 4, 5, 6 ! test pins 7 ! Ground pins commented by IPG test pins 8 test pins 13 ! test pins 14 ! Fix
20、ed pins commented by IPGdevice “u2” bottom; test pins 1 test pins 2 .,Turn On AutoDebug for iVTEP + VTEP,AutoDebug calculates the threshold limit,Before ADB,After ADB,The TestJet Test - After Debug,default threshold low 20 high 10000device “u1”; threshold low 15 high 10000 test pins 1 test pins 2, 3
21、; threshold low 350 high 10000 test pins 4, 5, 6; threshold low 450 high 10000 ! test pins 7 ! Ground pins commented by IPG test pins 8 ! test pins 13 ! Test measures 9 test pins 8 test pins 14 ! Fixed pins commented by IPGdevice “u2” bottom; test pins 1; threshold low 15 high 10000 test pins 2 test
22、 pins 3; threshold low 40 High 10000 .,Part 10,Overview of Boundary-Scan,Typical IC with Boundary-Scan,BoundaryCells,CoreLogic,Test DataIn (TDI),Test DataOut (TDO),Test ModeSelect (TMS),Test Clock(TCK),TEST ACCESS PORT CONTROLLER (TAP),The device can be controlledand tested through TDI, TCK,TMS, & T
23、DO,Arrows denote access points,Basic Test of IC with Boundary-Scan,The Boundary-Scan Test Development Process,Start with the BSDL file BSDL means Boundary-Scan Description Language” A language for describing the device specific characteristics of 1149.1 devices Language subset of VHDL Who will write
24、 BSDL ASIC designers Semiconductor vendors Test engineers,Typical IC with Boundary-Scan,Test DataIn (TDI),CoreLogic,TMS = Serial,Test Clock(TCK),TEST ACCESS PORT CONTROLLER (TAP),010101010101,101010,010101,010101,TMS = Parallel,TMS = Parallel,Typical IC with Boundary-Scan,Test DataIn (TDI),CoreLogic,TMS = Serial,Test Clock(TCK),TEST ACCESS PORT CONTROLLER (TAP),010101,010101,101010,101010,Thank you!,&More Questions ?,
