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1、AT89C2051 Microcontroller Instructions1.1 Features Compatible with MCS-51 Products 2 Kbytes of Reprogrammable Flash MemoryEndurance: 1,000 Write/Erase Cycles 2.7 V to 6 V Operating Range Fully Static Operation: 0 Hz to 24 MHz Two-Level Program Memory Lock 128 x 8-Bit Internal RAM 15 Programmable I/O
2、 Lines Two 16-Bit Timer/Counters Six Interrupt Sources Programmable Serial UART Channel Direct LED Drive Outputs On-Chip Analog Comparator Low Power Idle and Power Down Modes1.2 DescriptionThe AT89C2051 is a low-voltage, high-performance CMOS 8-bit microcomputer with 2 Kbytes of Flash programmable a
3、nd erasable read only memory (PEROM). The device is manufactured using Atmels high density nonvolatile memory technology and is compatible with the industry standard MCS-51 instruction set and pinout. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C2051 is a powerf
4、ul microcomputer which provides a highly flexible and cost effective solution to many embedded control applications.The AT89C2051 provides the following standard features: 2 Kbytes of Flash, 128 bytes of RAM, 15 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a
5、full duplex serial port, a precision analog comparator, on-chip oscillator and clock circuitry. In addition, the AT89C2051 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, t
6、imer/counters, serial port and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.1.3 Pin Configuration 1.4 Pin DescriptionVCC Supply voltage.GND Ground.Port 1Port 1 is an 8-
7、bit bidirectional I/O port. Port pins P1.2 to P1.7 provide internal pullups. P1.0 and P1.1 require external pullups. P1.0 and P1.1 also serve as the positive input (AIN0) and the negative input (AIN1), respectively, of the on-chip precision analog comparator. The Port 1 output buffers can sink 20 mA
8、 and can drive LED displays directly. When 1s are written to Port 1 pins, they can be used as inputs. When pins P1.2 to P1.7 are used as inputs and are externally pulled low, they will source current (IIL) because of the internal pullups.Port 1 also receives code data during Flash programming and pr
9、ogram verification.Port 3Port 3 pins P3.0 to P3.5, P3.7 are seven bidirectional I/O pins with internal pullups. P3.6 is hard-wired as an input to the output of the on-chip comparator and is not accessible as a general purpose I/O pin. The Port 3 output buffers can sink 20 mA. When 1s are written to
10、Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups. Port Pin Alternate FunctionsP3.0RXD (serial input port)P3.1TXD (serial output port)P3.2INT0 (external inte
11、rrupt 0)P3.3INT1 (external interrupt 1)P3.4T0 (timer 0 external input)P3.5T1 (timer 1 external input)Port 3 also serves the functions of various special features of the AT89C2051 as listed below:1.5 Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively, of an inverting amp
12、lifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements o
13、n the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divideby-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.1.6 Special Function RegistersA map of the on-chip memory area called the Special F
14、unction Register (SFR) space is shown in the table below. Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses. to these addresses will in general return random data, and write accesses will have an indeterminate effect.User soft
15、ware should not write 1s to these unlisted locations, since they may be used in future products to invoke new fea tures. In that case, the reset or inactive values of the new bits will always be 0.1.7 Restrictions on Certain InstructionsThe AT89C2051 and is an economical and cost-effective member of
16、 Atmels growing family of microcontrollers. It contains 2 Kbytes of flash program memory. It is fully compatible with the MCS-51 architecture, and can be programmed using the MCS-51 instruction set. However, there are a few considerations one must keep in mind when utilizing certain instructions to
17、program this device.All the instructions related to jumping or branching should be restricted such that the destination address falls within the physical program memory space of the device, which is 2K for the AT89C2051. This should be the responsibility of the software programmer. For example, LJMP
18、 7E0H would be a valid instruction for the AT89C2051 (with 2K of memory), whereas LJMP 900H would not.1. Branching instructions:LCALL, LJMP, ACALL, AJMP, SJMP, JMP A+DPTRThese unconditional branching instructions will execute correctly as long as the programmer keeps in mind that the destination bra
19、nching address must fall within the physical boundaries of the program memory size (locations 00H to 7FFH for the 89C2051). Violating the physical space limits may cause unknown program behavior.CJNE ., DJNZ ., JB, JNB, JC, JNC, JBC, JZ, JNZ With these conditional branching instructions the same rul
20、e above applies. Again, violating the memory boundaries may cause erratic execution.For applications involving interrupts the normal interrupt service routine address locations of the 80C51 family architecture have been preserved.2. MOVX-related instructions, Data Memory:The AT89C2051 contains 128 b
21、ytes of internal data memory. Thus, in the AT89C2051 the stack depth is limited to 128 bytes, the amount of available RAM. External DATA memory access is not supported in this device, nor is external PROGRAM memory execution. Therefore, no MOVX . instructions should be included in the program.A typi
22、cal 80C51 assembler will still assemble instructions, even if they are written in violation of the restrictions mentioned above. It is the responsibility of the controller user to know the physical features and limitations of the device being used and adjust the instructions used correspondingly.1.8
23、 Program Memory Lock BitsOn the chip are two lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below:Lock Bit Protection Modes(1) Program Lock BitsLB1LB2Protection Type1UUNo program lock features.2PUFurther programming of theF
24、lash is disabled.3PPSame as mode 2, also verifyis disabled.Note: 1. The Lock Bits can only be erased with the Chip Erase operation1.9 Idle ModeIn idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM a
25、nd all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset.P1.0 and P1.1 should be set to 0 if no external pullups are used, or set to 1 if external pullups are used.It should be noted that when idle is te
26、rminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate
27、the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.1.10 Power Down ModeIn the power down mode the oscillator is stopped, and the instruction that
28、invokes power down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power down mode is terminated. The only exit from power down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be ac
29、tivated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.P1.0 and P1.1 should be set to 0 if no external pullups are used, or set to 1 if external pullups are used.1.11 Programming The FlashThe AT89C2051 is ship
30、ped with the 2 Kbytes of on-chip PEROM code memory array in the erased state (i.e., contents = FFH) and ready to be programmed. The code memory array is programmed one byte at a time. Once the array is programmed, to re-program any non-blank byte, the entire memory array needs to be erased electrica
31、lly.Internal Address Counter: The AT89C2051 contains an internal PEROM address counter which is always reset to 000H on the rising edge of RST and is advanced by applying a positive going pulse to pin XTAL1.Programming Algorithm: To program the AT89C2051, the following sequence is recommended.1. Pow
32、er-up sequence:Apply power between VCC and GND pins Set RST and XTAL1 to GNDWith all other pins floating, wait for greater than 10 milliseconds2. Set pin RST to H Set pin P3.2 to H3. Apply the appropriate combination of H or L logic levels to pins P3.3, P3.4, P3.5, P3.7 to select one of the programm
33、ing operations shown in the PEROM Programming Modes table.To Program and Verify the Array:4. Apply data for Code byte at location 000H to P1.0 to P1.7. 5. Raise RST to 12V to enable programming.6. Pulse P3.2 once to program a byte in the PEROM array or the lock bits. The byte-write cycle is self-tim
34、ed and typically takes 1.2 ms.7. To verify the programmed data, lower RST from 12V to logic H level and set pins P3.3 to P3.7 to the appropiate levels. Output data can be read at the port P1 pins.8. To program a byte at the next address location, pulse XTAL1 pin once to advance the internal address
35、counter. Apply new data to the port P1 pins.9. Repeat steps 5 through 8, changing data and advancing the address counter for the entire 2 Kbytes array or until the end of the object file is reached.10. Power-off sequence: set XTAL1 to L set RST to LFloat all other I/O pins Turn Vcc power offData Pol
36、ling: The AT89C2051 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written data on P1.7. Once the write cycle has been completed, true data is valid on all outputs, and the next cycle m
37、ay begin. Data Polling may begin any time after a write cycle has been initiated.Ready/Busy: The Progress of byte programming can also be monitored by the RDY/BSY output signal. Pin P3.1 is pulled low after P3.2 goes High during programming to indicate BUSY. P3.1 is pulled High again when programmin
38、g is done to indicate READY.Program Verify: If lock bits LB1 and LB2 have not been programmed code data can be read back via the data lines for verification:1. Reset the internal address counter to 000H by bringing RST from L to H.2. Apply the appropriate control signals for Read Code data and read
39、the output data at the port P1 pins.3. Pulse pin XTAL1 once to advance the internal address counter.4. Read the next code data byte at the port P1 pins. 5. Repeat steps 3 and 4 until the entire array is read.The lock bits cannot be verified directly. Verification of the lock bits is achieved by obse
40、rving that their features are enabled.Chip Erase: The entire PEROM array (2 Kbytes) and the two Lock Bits are erased electrically by using the proper combination of control signals and by holding P3.2 low for 10 ms. The code array is written with all 1s in the Chip Erase operation and must be execut
41、ed before any non-blank memory byte can be re-programmed.Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 000H, 001H, and 002H, except that P3.5 and P3.7 must be pulled to a logic low. The values returned are as follows.(000H) = 1E
42、H indicates manufactured by Atmel (001H) = 21H indicates 89C2051Programming InterfaceEvery code byte in the Flash array can be written and the entire array can be erased by using the appropriate combination of control signals. The write operation cycle is self-timed and once initiated, will automati
43、cally time itself to completion.All major programming vendors offer worldwide support for the Atmel microcontroller series. Please contact your local programming vendor for the appropriate software revision.AT89C2051微控制器的指令一、特点 兼容MCS - 51产品 2个字节的可再编程闪存 待添加的隐藏文字内容3耐力擦写/擦除周期 2. 7 V至6 V工作范围 全静态操作0 Hz至2
44、4 MHz的 两级程序存储器锁定 128 8位内部RAM 15个可编程I / O线 2个16位定时器/计数器 六个中断源 可编程串行UART通道 直接LED驱动输出 片上模拟比较器 低功耗空闲和掉电模式 二、说明 该AT89C2051是一个低电压，高性能CMOS 8位2 Kby 的Flash可编程，可擦除只读存储器（PEROM）设备是制造 tured采用Atmel的高密度非易失性内存技术，并与兼容的工商业污水附加费微机工业标准MCS - 51指令集，并通过结合在一个通用的单芯片闪存的8位CPU引脚，Atmel的AT89C2051是一种功能强大的微机提供了高度灵活和成本效益的解决方案，许多嵌入式
45、控制应用 该AT89C2051提供以下标准功能2字节的闪存，128字节RAM，15 I / O线，两个16位定时器/计数器，一个五向量2级中断结构，一个全双工串行口，一个精密模拟比较器，片上振荡器和时钟电路此外，该AT89C2051的设计与操作频率下降到零静态逻辑，支持两种软件可选的节电模式空闲模式时CPU停止工作，同时允许RAM，定时/计数器，串行口和中断系统继续工作暂停模式保存RAM的内容，但冻结，直到下一个硬件复位振荡器禁用所有其他芯片功能 三、引脚配置四、引脚说明 VCC电源电压 GND接地 端口1 端口1是一个8位双向I / O端口端口引脚P1 2至7提供P1 P1和P1 0 1 0
46、内部上拉需要P1和P1 1外部上拉也可作为正输入（AIN0）和负输入（AIN1 ），分别对片内精密模拟比较器的端口1输出缓冲器可以吸收20mA的电流，并且可以直接驱动LED时1秒写入端口1引脚，它们可以作为输入引脚P1 2时至P17顷作为输入，并从外部拉低，将输出电流（IIL）由于内部上拉在端口1也接收片内Flash存储。端口3 P3口P3 0至5 P3，P37顷带有内部上拉P3 6 seven双向I / O引脚是作为对片上比较器输出输入硬连接，而不是作为一个通用访问构成我/ O引脚的3口输出缓冲器可吸收20mA当1秒写入端口3他们拉高内部上拉，可作为作为输入，3口被外部拉低的引脚为低电平输入
47、的引脚将输出电流（ IIL）由于上拉在端口3也接收片内Flash存储。 端口引脚的第二功能 P3 0 RXD（串行输入口） P3 1 TXD（串行输出端口）P3 2 INT0（外部中断0）P3 3 INT1（外部中断1） P3 4 T0（定时器0外部输入）端口3也可以用下面列出的AT89C2051各种特殊功能， 五、振荡器特性 XTAL1和XTAL2分别是输入和输出，分别为一个反相放大器，可用于作为一个片上振荡器使用配置，如图1无论是石英晶体或陶瓷谐振器可用于驱动外部显示设备时钟源，XTAL2应悬空而XTAL1驱动，如图2所示有没有重新 quirements对外部时钟信号的占空比，由于内部时钟
48、电路的输入通过鸿沟由二翻转翻牌，但最小和最大电压高和低时间规范必须遵守。 六、特殊功能寄存器 一个片上内存区域的地图称为特殊功能寄存器（SFR）空间中的表所示请注意，并非所有的地址都被占用，并无人居住地址可能无法在芯片上实现的读取访问这些地址。七、某些指令的限制 该AT89C2051是一种经济和成本效益的纪念品， Atmel的越来越多的微控制器系列。BER它包含2闪存程序存储器，是完全与MCS - 51架构兼容，并能进行编程使用。MCS - 51指令集然而，也有少数的审议操作之一时，必须牢记某些指令计划利用此装置有关的所有分支指令跳跃或应限制在物理方案的设备，这是2K的AT89C2051。这应该是软的责任软件例如程序员的内存空间，这样的目标地址瀑布，LJMP 7E0H会是为AT89C2051（2K的内存）有效指令，而LJMP 900H不会1分支指令 。LCALL，LJMP，A
