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1、外文文献1原文：DDS devices to produce high-quality waveform: a simple, efficient and flexibleSummaryDirect digital frequency synthesis (DDS) technology for the generation and regulation of high-quality waveforms, widely used in medical, industrial, instrumentation, communications, defense and many other ar
2、eas. This article will briefly describe the technology, on its strengths and weaknesses, examine some application examples, and also introduced some new products that contribute to the promotionIntroductionA key requirement in many industries is an exact production, easy operation and quick change o
3、f different frequencies, different types of waveforms. Whether it is broadband transceiver requires low phase noise and excellent spurious-free dynamic performance of agile frequency source, or for industrial measurement and control system needs a stable frequency excitation, fast, easy and economic
4、al to produce adjustable waveform while maintaining phase continuity capabilities are critical to a design standard, which is what the advantages of direct digital frequency synthesis.Frequency synthesis taskThe growing congestion of the spectrum, coupled with lower power consumption, quality of nev
5、er-ending demand for higher measuring equipment, these factors require the use of the new frequency range, requires a better use of existing frequency range. A result, the search for better control, in most cases, by means of frequency synthesizer for frequency generation. These devices use a given
6、frequency, fC of to generate a target frequency (and phase) fOUT the general relationship can be simply expressed as:fOUT = x fCAmong them, the scale factor x, sometimes known as the normalized frequency.The equation is usually gradual approximation of the real number algorithms. When the scale fact
7、or is a rational number, two relatively prime numbers (output frequency and reference frequency) than the harmonic. However, in most cases, x may belong to a broader set of real numbers, the approximation process is within the acceptable range will be truncatedDirect Digital Frequency SynthesizerThe
8、 frequency synthesizer a practical way to achieve is the direct digital frequency synthesis (of DDFS), usually referred to as direct digital synthesis (DDS). This technique using digital data processing to generate a frequency and phase adjustable output, the output anda fixed frequency reference cl
9、ock source fC. related. DDS architecture, the reference or the system clock frequency divided by a scale factor to produce the desired frequency, the scale factor is controlled by the binary tuning word programmable.In short, direct digital frequency synthesizer to convert a bunch of clock pulses in
10、to an analog waveform, usually a sine wave, triangle wave or square wave. Shown in Figure 1, its main parts: the phase accumulator (to produce the output waveform phase angle data), relative to digital converter, (above the phase data is converted to the instantaneous output amplitude data), and dig
11、ital-to-analog converter (DAC) (the magnitude of data into a sampled analog data points)Figure 1.DDS function of the system block diagram.For the sine wave output, relative to digital converter is usually a sine lookup table (Figure 2). Phase accumulator unit count N a relative to the frequency of f
12、C, according to the following equation:The number of pulses of the fC:M is the resolution of the tuning word (24-48) N corresponds to the smallest increment of phase change of the phase accumulator output wordFigure 2. Typical DDS architecture and signal path (with DACs).Changing N will immediately
13、change the output phase and frequency, so the system has its own continuous phase characteristics, which is one of the key attributes of many applications. No loop settling time, which is different from the analog system, such as phase-locked loops (PLLs). DAC is usually a high-performance circuit,
14、designed specifically for the DDS core (phase accumulator and phase amplitude converter). In most cases, the results of the device (usually single-chip) is generally referred to as the pure DDS or the C-DDS.Actual DDS devices are generally multiple registers, in order to achieve a different frequenc
15、y and phase modulation scheme. Such as phase register, their storage phase of increase in the output phase of the phase accumulator. In this way, the corresponding delay output sine wave phase in a phase tuning word. This is useful for phase modulation applications for communication systems. The res
16、olution of the adder circuit determines the number of bits of the phase tuning word, therefore, also decided to delay the resolution.Integrated in a single device on the engine of a DDS and a DAC has both advantages and disadvantages, however, whether integrated or not, need a DAC to produce ultra-h
17、igh purity high-quality analog signal. DAC will convert digital sinusoidal output to an analog sine wave may be single-ended or differential. Some of the key requirements for low phase noise, excellent wideband (WB) and narrowband (NB), spurious-free dynamic range (SFDR), and low power consumption.
18、If the external device, the DAC must be fast enough to handle the signal, so the built-in parallel port device is very common.DDS and other solutionsThe frequency analog phase-locked loops (PLLs), clock generator, and the use of FPGA dynamic programming of the output of the DAC. By examining the spe
19、ctrum of performance and power of these technologies, a simple comparison, Table 1 shows the qualitative results of the comparisonTable 1.DDS with competing technologies - Advanced compare Power consumptionSpectral purityRemarksDDSLowMiddleEase of tuningDiscrete DAC+FPGAMiddleMiddle-HighWith tuning
20、capabilitiesAnalog PLLMilddleHighDifficult tuningPhase-locked loop is a feedback loop and its components: a phase comparator, a divider and a pressure-controlled oscillator (VCO), phase comparator reference frequency and output frequency (usually the output frequency is N)frequency) were compared. T
21、he error voltage generated by the phase comparator is used to adjust the VCO, thus the output frequency. When the loop is established, the output frequency and / or phase with the reference frequency to maintain a precise relationship. PLL has long been considered in a particular frequency range, hi
22、gh fidelity and consistent signal low phase noise and high spurious free dynamic range (SFDR) are ideal for applications. PLL can not be precisely and quickly tuning the frequency output waveform, and the slow response, which limits their applicability for fast frequency hopping and part of the freq
23、uency shift keying and phase shift keying applications. Other programs, including integrated DDS engine field programmable gate arrays (FPGAs) - a synthetic sine wave output with the off-the-shelf DAC - though the PLL frequency-hopping problem can be solved, but there own shortcomings. The defects o
24、f the major systems work and interface power requirements, high cost, large size, and system developers must also consider the additional software, hardware and memory. For example, using the DDS engine option in the modern FPGA to generate the 10 MHz output signal dynamic range is 60 dB up to 72 kB
25、 memory space. In addition, designers need to accept and be familiar with the subtle balance DDS core architecture. .From a practical point of view (see Table 2), thanks to the rapid development of CMOS technology and modern digital design techniques, as well as the improvement of the DAC topology,
26、DDS technology has been able to achieve unprecedented low power consumption in a wide range of applications, spectrum performance and cost levels. Although the pure DDS products in performance and design flexibility to achieve the level of high-end DAC technology and FPGA, but the advantages of DDS
27、in terms of size, power consumption, cost and simplicity, making it the primary choice for many applications.Table 2 Benchmark Analysis Summary - frequency generation technique (50 MHz) Phase -locked loopDAC + FPGADDSSpectral performanceHighHighMiddleSystem power requirementsHighHighMiddleDigital fr
28、equency tuningNoYesYesTuning response timeHighLowLowSolution sizeMiddleHighLowWaveform flexibilityLowMiddleHighCostMiddleHighLowDesign reuseMiddleLowHighImplementation complexityMiddleHighLowAlso be noted that the DDS device for digital methods to produce the output waveform, it can simplify some of
29、 the architecture of the solution, or the waveform of digital programming to create the conditions. Usually with a sine wave to explain the functions and working principle of the DDS, but using modern DDS ICs can easily generate a triangle wave or square wave (clock) output, thereby eliminating the
30、former case the lookup table, and the latter case the DAC the need to integrate a simple and accurate enough.Performance and limitations of the DDSImage and envelope: Sin (x) xx roll-offThe actual output of the DAC is not a continuous sine wave, but a series of pulses with a sinusoidal time envelope
31、. The corresponding spectrum is a series of image and signal aliasing. Image along the sin (x) / x envelope distribution (see Figure 3 | margin | graph). The need for the filter to suppress frequencies outside the target band, but can not inhibit the high-level in the passband aliasing (for example,
32、 caused due to DAC non-linear)The Nyquist criterion requires that each cycle requires at least two sampling points in order to rebuild the desired output waveform. The Mirroring response arising from sampling the output frequency K, CLOCK OUT In this example, which CLOCK = 25 25 MHz and fOUT = 5 MHz
33、, the first and second mirror frequency appear in (see Figure 3) fCLOCK fOUT, o 20 MHz and 30 MHz. The third and fourth mirror frequency at 45 MHz and 55 MHz. Note, sin (x) / x value of zero at multiples of the sampling frequency. When fOUT greater than the Nyquist bandwidth (1/2 f CLOCK), the first
34、 mirror frequency will appear in the Nyquist bandwidth, the occurrence of aliasing (such as 15 MHz signal aliasing down to 10 MHz). Can not use the traditional quist anti-aliasing filter to filter out aliasing mirror frequency from the outputSin, in Figure 3.DDS, (x) / x roll-off.In a typical DDS ap
35、plication, the use of a low-pass filter to suppress the mirror frequency response of the output spectrum. To make the low-pass filter cutoff frequency to remain at reasonable levels, and keep it simple filter design, a feasible approach is the use of an economic low-pass output filter bandwidth limi
36、ted to about 40% of the frequency of clock.Any given mirror frequency relative to the amplitude of the fundamental formula of sin (x) / x calculation. Because the function of the frequency roll-off, the basic output of the amplitude and the output frequency is inversely proportional to decrease; in
37、the DDS system, reduce the amount of DC-Nyquist bandwidth range of -3.92 dB.Significant reduction in frequency in the first mirror - the fundamental 3 dB range. In order to simplify the DDS application filtering, frequency plan must be formulated and analyzed to mirror the frequency and magnitude of
38、 the sin (x) / x response in the OUT and CLOCK target frequency spectrum requirements. Other unwanted frequencies in the output spectrum (such as integral and differential linearity error of the DAC, the surge of energy associated with the DAC and clock feed through noise) does not follow the sin (x
39、) / x roll-off response. These unwanted frequencies will be harmonic and spurious energy in the output spectrum in many places - but its magnitude is generally far below the mirror frequency response. DDS devices to the general background noise, substrate noise, thermal noise effects, ground couplin
40、g and other signal source coupling factor cumulative portfolio decisions. DDS devices, the noise floor performance of stray and jitter by the circuit board layout, power quality, and - most importantly - Enter the profound impact of the quality of the reference clock.ShakeThe edge of the perfect clo
41、ck source will be the precise time interval, the interval will never change. Of course, this is not possible; even the best oscillator is also the ideal components constitute, with noise and other defects. Quality and low phase noise crystal oscillator jitter picosecond, and is built up from one mil
42、lion the number of clock edge. The factors leading to jitter external interference, thermal noise, the oscillator circuit instability and power, ground and output connections bring, all these factors will interfere with the timing characteristics of the oscillator. In addition, the oscillator by the
43、 external magnetic field or electric field and the nearby transmitter RF interference. Oscillator circuit, a simple amplifier, inverter or buffer to signal additional jitter.Therefore, the choice of a low-jitter, and the edge of steep stable reference clock oscillator is critical. Higher frequency r
44、eference clock allows a larger sample, and divide to some extent, reduce the jitter, because the signal to divide a long time to produce the same amount of jitter, which can reduce the jitter on the signal percentage.Noise - including the phase noiseThe sampling system noise depends on many factors,
45、 the most important factor is the reference clock jitter, this jitter performance of phase noise on fundamental signal. In the DDS system, the register output of the truncated phase may bring the system error code. The binary word does not lead to the truncation error. But for non-binary word, phase
46、 noise truncation error in the spectrum spurious. Spurious frequency / amplitude depends on the code word. Quantification and linearity error of the DAC will be brought to the system harmonic noise. Time-domain error (such as owed to the red / overshoot and code errors) will increase the output sign
47、al distortion.ApplicationDDS applications can be divided into two categories:Require agile frequency source for data coding and modulation applications, communications and radar systemsRequire measurement of the universal frequency synthesizer features and programmable tuning, scanning, and motivati
48、onal skills, industrial and optical applicationsBoth cases, the trend toward higher spectral purity (low phase noise and higher spurious free dynamic range), also low power and small size requirements to accommodate the remote ordemand for battery-powered devices.Modulation / data encoding, and sync
49、hronization of the DDSDDS products first appeared on the radar and military applications and the development of some of its characteristics (performance improvements, cost and size, etc.) DDS technology is becoming more prevalent in the modulation and data encoding applications. This section will discuss the two data encoding scheme in the DDS system.Binary f
