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1、 译 文 原文题目： A5191HRT AMIS HART Modem 译文题目： A5191HRT型HART调制解调器 学 院： 电子信息学院 专业班级： 自动化2009级04班 学生姓名： 学 号： 40905010435 A5191HRT AMIS HART Modem1. FeaturesCan be used in designs presently using the SYM20C15Single-chip, half-duplex 1200 bits per second FSK modemBell 202 shift frequencies of 1200Hz and 2200
2、Hz3.3V - 5.0V power supplyTransmit-signal wave shapingReceive band-pass filterLow power: optimal for intrinsically safe applicationsCMOS compatibleInternal oscillator requires 460.8kHz crystal or ceramic resonatorMeets HART physical layer requirementsIndustrial temperature range of -40C to +85CAvail
3、able in 28-pin PLCC and 32-pin LQFP packages2. DescriptionThe A5191HRT is a single-chip, CMOS modem for use in highway addressable remote transducer (HART) field instruments and masters. The modem and a few external passive components provide all of the functions needed to satisfy HART physical laye
4、r requirements including modulation, demodulation, receive filtering, carrier detect, and transmit-signal shaping. The A5191HRT is pin-compatible with the SYM20C15. See the Pin Description and Functional Description sections for details on pin compatibility with the SYM20C15.The A5191HRT uses phase
5、continuous frequency shift keying (FSK) at 1200 bits per second. To conserve power the receive circuits are disabled during transmit operations and vice versa. This provides the half-duplex operation used in HART communications.Figure 2-1 28-Pin PLCC Pinout Diagrams (green & non-green)Figure 2-2 32-
6、Pin LQFP Pinout Diagrams (green & non-green)Table 2-1 Pinout Summary 28-Pin PLCC, A5191HRTP/Pg (12197-504/508)Pin N0.Signal NameTypePin description1TEST1InputConnect to VSS2TEST2-No connect3TEST3-No connect4TEST4-No connect5TEST5InputConnect to VSS6INRESETInputReset all digital logic when low7TEST7I
7、nputConnect to VSS8TEST8InputConnect to VSS9TEST9InputConnect to VSS10OTXAOutputOutput transmit analog, FSK modulated HART transmit signal to 4-20mA loop interface circuit11IAREFInputAnalog reference voltage12ICDREFInputCarrier detect reference voltage13OCBIASOutputComparator bias current14TEST10Inp
8、utConnect to VSS15VDDAPowerAnalog supply voltage16IRXAInputFSK modulated HART receive signal from 4-20mA loop interface circuit17ORXAFOutputAnalog receive filter output18IRXACInputAnalog receive comparator input19OXTLOutputCrystal oscillator output20IXTLInputCrystal oscillator input21VSSGroundGround
9、22VDDPowerDigital supply voltage23INRTSInputRequest to sent24ITXDInputInput transmit date, transmitted HART data stream from UART25TEST11-No connect26ORXDOutputReceived demodulated HART data to UART27OCDOutputCarrier detect output28TEST12-No connectTable 2-2 Pinout Summary 32-Pin LQFP, A5191HRTL/Lg
10、(12197-503/507)Pin No.Signal NameTypePin Description1TEST5InputConnect to VSS2INRESETInputReset all digital logic when low, connect to VDD for normal operation3TEST7InputConnect to VSS4TEST8InputConnect to VSS5TEST9InputConnect to VSS6VSSGroundDigital ground7OTXAOutputOutput transmit analog, FSK mod
11、ulated HART transmit signal to 4-20mA loop interface circuit8IAREFInputAnalog reference voltage9ICDREFInputCarrier detect reference voltage10OCBIASOutputComparator bias current11TEST10InputConnect to VSS12VSSAGroundAnalog ground13VDDAPowerAnalog supply voltage14IRXAInputFSK modulated HART receive si
12、gnal from 4-20mA loop interface circuit15ORXAFOutputAnalog receive filter output16IRXACInputAnalog receive comparator input17OXTLOutputCrystal oscillator output18IXTLInputCrystal oscillator input19VSSAGroundAnalog ground20VSSGroundDigital ground21VDDPowerDigital supply voltage22INRTSInputRequest to
13、send23ITXDInputInput transmit data, transmitted HART data stream from UART24TEST11-No connect25ORXDOutputReceived demodulated HART data to UART26OCDOutputCarrier detect output27TEST12-No connect28TEST1InputConnect to VSS29TEST2-No connect30VDDPowerDigital supply voltage31TEST3-No connect32TEST4-No c
14、onnect3. Pin DescriptionsTable 3-1 Pin DescriptionsSymbolPin NameDescriptionIAREFAnalog Reference VoltageAnalog input sets the dc operating point of the operational amplifiers and comparators and is usually selected to split the dc potential between VDD and VSS. ICDREFCarrier Detect Reference Voltag
15、eAnalog input controls at which level the carrier detect (OCD) becomes active. This is determined by the dc voltage difference between ICDREF and IAREF. Selecting ICDREF - IAREF equal to 0.08 VDC will set the carrier detect to a nominal 100 mVp-pINRESETReset Digital LogicWhen at logic low (VSS) this
16、 input holds all the digital logic in reset. During normal operation INRESET should be at VDD. INRESET should be held low for a minimum of 10nS after VDD = 2.5V as shown in Figure 3INRTSRequest to SendActive-low input selects the operation of the modulator. OTXA is enabled when this signal is low. T
17、his signal must be held high during power-upIRXAAnalog Receive InputInput accepts the 1200/2200Hz signals from the external filterIRXACAnalog Receive Comparator InputPositive input of the carrier detect comparator and the receiver filter comparatorITXDDigital Transmit Input (CMOS)Input to the modula
18、tor accepts digital data in NRZ form. When ITXD is low, the modulator output frequency is 2200Hz. When ITXD is high, the modulator output frequency is 1200Hz.IXTLOscillator InputInput to the internal oscillator must be connected to a parallel mode 460.8kHz ceramic resonator when using the internal o
19、scillator or grounded when using an external 460.8kHz clock signalOCBIASComparator Bias CurrentThe current through this output controls the operating parameters of the internal operational amplifiers and comparators. For normal operation, OCBIAS current is set to 2.54A.OCDCarrier Detect OutputOutput
20、 goes high when a valid input is recognized on IRXA. If the received signal is greater than the threshold specified on ICDREF for four cycles of the IRXA signal, the valid input is recognized.ORXAFAnalog Receive Filter OutputSignal is the square wave output of the receiver high-pass filterORXDDigita
21、l Receive Output (CMOS)Signal outputs the digital receive data. When the received signal (IRXA) is 1200Hz, ORXD outputs logic high. When the received signal (IRXA) is 2200Hz, ORXD outputs logic low. ORXD is qualified internally with OCD.OTXAAnalog Transmit OutputOutput provides the trapezoidal signa
22、l controlled by ITXD. When ITXD is low, the output frequency is 2200Hz. When ITXD is high, the output frequency is 1200Hz. This output is active when INRTS is low and 0.5 VDC when INRTS is high.OXTLOscillator OutputOutput from the internal oscillator must be connected to an external 460.8kHz clock s
23、ignal or to a parallel mode 460.8kHz ceramic resonator when using the internal oscillatorTEST(12:1)Factory TestFactory test pins; for normal operation, tie these signals as per Table 1 and Table 2VDDDigital PowerPower for the digital modem circuitryVDDAAnalog Supply VoltagePower for the analog modem
24、 circuitryVSSGroundAnalog and digital groundVSSAAnalog GroundFigure 3-1 Reset TimingNote:This signal is also present on the LSI 20C15. It is labeled as Test6. The 20C15 data sheet mentions the reset function of this pin but does not emphasize its use to reset the chip. Reliable operation of the mode
25、m requires a hardware reset as shown in Figure 3. This is true for the AMIS 12197-503 and 12197-504 as well as the LSI 20C15.4. Functional DescriptionThe A5191HRT is a functional equivalent of the SYM20C15 HART Modem. It contains a transmit data modulator and signal shaper, carrier detect circuitry,
26、 analog receiver and demodulator circuitry and an oscillator, as shown in Figure 4-1. The internal HART modem modulates the transmit-signal and demodulates the receive signal. The transmit-signal shaper enables the A5191HRT to transmit a HART compliant signal. The carrier is detected by comparing th
27、e receiver filter output with the difference between two external voltage references. The analog receive circuitry band-pass filters the received signal for input to the modem and the carrier detect circuitry. The oscillator provides the modem with a stable time base using either a simple external r
28、esonator or an external clock source. Figure 4-1 A5191HRT Block Diagram4.1 A5191HRT LogicThe modem consists of a modulator and demodulator. The modem uses shift frequencies of nominally 1200Hz (for a 1) and 220Hz (for a 0). The bit rate is 1200 bits/second.4.1.1 ModulatorThe modulator accepts digita
29、l data in NRZ form at the ITXD input and generates the FSK modulated signal at the OTXA output. INRTS must be a logic low for the modulator to be active.4.1.2 DemodulatorThe demodulator accepts an FSK signal at the IRXA input and reproduces the original modulating signal at the ORXD output. The nomi
30、nal bit rate is 1200 bits per second. Figure 4-2 illustrates the demodulation process.Figure 4-2 Demodulator Signal Timing The output of the demodulator is qualified with the carrier detect signal (OCD), therefore, only IRXA signals large enough to be detected (100mVp-p typically) by the carrier det
31、ect circuit produce received serial data at ORXD.Maximum demodulator jitter is 12 percent of one bit given input frequencies within HART specifications, a clock frequency of 460.8kHz (1.0 percent) and zero input (IRXA) asymmetry.4.2 Transmit-Signal ShaperThe transmit-signal shaper generates a HART c
32、ompliant FSK modulated signal at OTXA. Figure 4-3 and Figure 4-4 show the transmit-signal forms of the A5191HRT.For IAREF = 1.235 VDC, OTXA will have a voltage swing from approximately 0.25 to 0.75 VDC.Figure 4-3 OTXA Waveform (1200Hz) Figure 4-4 OTXA Waveform (2200Hz)4.3 Carrier Detect CircuitryThe
33、 carrier detect comparator shown in Figure 4-5 generates logic low output if the IRXAC voltage is below ICDREF. The comparator output is fed into a carrier detect block (see Figure 4). The carrier detect block drives the carrier detect output pin OCD high if INRTS is high and four consecutive pulses
34、 out of the comparator have arrived. OCD stays high as long as INRTS is high and the next comparator pulse is received in less than 2.5ms. Once OCD goes inactive, it takes four consecutive pulses out of the comparator to assert OCD again. Four consecutive pulses amount to 3.33ms when the received si
35、gnal is 1200Hz and to 1.82ms when the received signal is 2200HZ.4.4 Analog Receiver Circuitry4.4.1 Voltage ReferencesThe A5191HRT requires two voltage references, IAREF and ICDREF. IAREF sets the dc operating point of the internal operational amplifiers and comparators. A 1.235 VDC reference (Analog
36、 Devices AD589) is suitable as IAREF.The level at which OCD (carrier detect) becomes active is determined by the dc voltage difference (ICDREF - IAREF). Selecting a voltage difference of 0.08 VDC will set the carrier detect to a nominal 100 mVp-p.4.4.2 Bias Current ResistorThe A5191HRT requires a bi
37、as current resistor to be connected between OCBIAS and VSS. The bias current controls the operating parameters of the internal operational amplifiers and comparators.The value of the bias current resistor is determined by the reference voltage IAREF and the following formula:The recommended bias cur
38、rent resistor is 500K when IAREF is equal to 1.235 VDC.In Figure 4-5 all external capacitor values have a tolerance of 5 percent and the resistors have a tolerance of 1 percent, except the 3M which has a tolerance of 5 percent. External to the A5191HRT, the filter exhibits a three-pole, high-pass fi
39、lter at 624Hz and a one-pole, low-pass filter at 2500Hz. Internally, the A5191HRT has a high-pass pole at 35Hz and a low-pass pole at 90kHz. The low-pass pole can vary as much as 30 percent. The input impedance of the entire filter is greater than 150M at frequencies below 50kHz.Figure 4-5 Receive F
40、ilter Schematic 4.5 OscillatorThe A5191HRT requires a 460.8kHz clock signal on OXTL. This can be provided by an external clock or external components may be connected to the A5191HRT internal oscillator.4.5.1 Internal Oscillator OptionThe oscillator cell will function with either a 460.8kHz crystal
41、or ceramic resonator. A parallel resonant ceramic resonator can be connected between OXTL and IXTL. Figure 4-6 illustrates the crystal option for clock generation using a 460.8kHz (I percent tolerance) parallel resonant crystal and two tuning capacitors. The actual values of the capacitors may depen
42、d on the recommendations of the manufacturer of the resonator. Typically, capacitors in the range of 100pF to 470pF are used.4.5.2 External Clock OptionIt may be desirable to use an external 460.8kHz clock as shown in Figure 4-7rather than the internal oscillator because of the high cost and low ava
43、ilability of ceramic resonators. In addition, the A5191HRT consumes less current when an external clock is used. Minimum current consumption occurs with the clock connected to OXTL and IXTL connected to VSS.Figure 4-6 Crystal OscillatorFigure 4-7 Oscillator with External ClockA5191HRT型HART调制解调器1. 主要
44、特点可用于设计目前正在使用的SYM20C15单芯片，半双工1200 bits调制解调器每秒FSK贝尔202的1200Hz和2200Hz移频3.3V - 5.0V电源发送信号波形整形接收频带通滤波器低功耗：为本质安全应用的最佳选择CMOS兼容内部振荡器需要460.8kHz 晶体或陶瓷谐振器符合HART协议物理层要求工业温度范围为-40C +85C可在28-pin PLCC和32-pin LQFP包2. 描述A5191HRT是一款具有CMOS调制解调器的单片机，可用于HART协议领域中的仪器和高端仪器。调制解调器和几个外部无源元件提供了所有用于满足HART协议物理层需要的功能，包括调制、解调、接收
45、滤波器、载波检测电路、发送信号整形电路。A5191HRT型是sym20c15的引脚兼容。sym20c15引脚兼容详情见引脚描述和功能描述。A5191HRT使用连续周期的移频键控，频率为1200b/s。为了节省电能，接收电路期间禁用发送操作，反之亦然。这提供了用于HART通信的半双工操作。图2-1 28-Pin PLCC引脚输出图（绿色和非绿色）图 2-2 32-Pin LQFP引脚输出图（绿色和非绿色）表2-1 28引脚引脚输出功能，A5191HRTP/Pg (12197-504/508)引脚号信号名称类型引脚说明1TEST1输入连接到VSS2TEST2-无连接3TEST3-无连接4TEST4-无连接5TEST5输入连接到VSS6INRESET输入复位时，所有的数字逻辑低7TEST7输入连接到VSS8TEST8输入连接到VSS9TEST9输入连接到VSS10OTXA输出输出传输模拟，FSK调制的HART信号传输到接口电路回路4-20mA11IAREF输入模拟参考电压12ICDREF输入载波参考电压检测13OCBIAS输出当前比较偏置14TEST10输入
