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1、SPCE061A 32K x 16 SOUND CONTROLLER1. GENERAL DESCRIPTIONThe SPCE061A, a 16-bit architecture product, carries the newest 16-bit microprocessor, nSP (pronounced as micro-n-SP), developed by Sunplus Technology. This high processing speed assures the nSP is capable of handling complex digital signal pro
2、cesses easily and rapidly. Therefore, the SPCE061A is applicable to the areas of digital sound process and voice recognition. The operating voltage of 3.0V through 3.6V and speed of 0.32MHz through 49.152MHz yield the SPCE061A to be easily used in varieties of applications. The memory capacity inclu
3、des 32K-word flash memory plus a 2K-word working SRAM. Other features include 32 programmable multi-functional I/Os, two 16-bit timers/counters, 32768Hz Real Time Clock, Low Voltage Reset/Detection, eight channels 10-bit ADC (one channel built-in MIC amplifier with auto gain controller), 10-bit DAC
4、output and many others.BLOCK DIAGRAM3. FEATURES 16-bit nSP microprocessor CPU clock: 0.32MHz - 49.152MHz Operating voltage: 3.0V - 3.6V Program Flash Operating voltage: 3.0V - 3.6V IO PortA & B operating voltage: 3.0V - 5.5V 32K-word flash
5、memory 2K-word working SRAM Software-based audio processing Crystal Resonator Standby mode (Clock Stop mode) for power savings, Max. 2.0A VDD = 3.6V Two 16-bit timers/counters Two 10-bit DAC outputs 32 general I/Os (bit programmab
6、le) 14 INT sources with two priority levels Key wakeup function (IOA0 - 7) Approx. 190 sec speech 2.0Kbit/per sec with SACM_S200 PLL feature for system clock 32768Hz Real Time Clock (RTC) Eight channels 10-bit AD converter ADC ext
7、ernal top reference voltage 2.0V voltage regulator output, 5mA of driving capability Serial interface I/O (SIO) Built-in microphone amplifier and AGC function UART receiver and transmitter (full duplex) Low voltage reset and low voltage detection
8、48708; Watchdog enable (bonding option) ICE function for development and down load into flash memory Security function to protect code to be read and written.4. APPLICATION FIELD Voice recognition products Intelligent interactive talking toys Advance
9、d educational toys Kids learning products Kids storybook General speech synthesizer Long duration audio products Recording / playback productsSIGNAL DESCRIPTIONS5. FUNCTIONAL DESCRIPTIONS5.1. CPUThe SPCE061A is equipped with a 16-bit nSP, the newest
10、16-bit microprocessor by Sunplus and pronounced as micro-n-SP. Eight registers are involved in nSP: R1 - R4 (General-purpose registers), PC (Program Counter), SP (Stack Pointer), Base Pointer (BP) and SR (Segment Register). The interrupts include three FIQs (Fast Interrupt Request) and eight IRQs (I
11、nterrupt Request), plus one software-interrupt, BREAK.Moreover, a high performance hardware multiplier with the capability of FIR filter is also built in to reduce the software multiplication loading.5.2. Memory5.2.1. SRAMThe amount of SRAM is 2K-word (including Stack), ranged from $0000 through $07
12、FF with access speed of two CPU clock cycles.5.2.2. Flash memoryFlash memory ($008000 $00FFFF) is a high-speed memory with access speed of two CPU clock cycles. FLASH erase and program functions must be used in IDE tools.5.3. PLL, Clock, Power Mode5.3.1. PLL (Phase Lock Loop)The purpose of PLL is to
13、 provide a base frequency (32768Hz) and to pump the frequency from 20.48MHz to 49.152MHz for system clock (Fosc). The default PLL frequency is 24.576MHz.5.3.1.1. System clockBasically, the system clock is provided by PLL and programmed by the Port_SystemClock (W) to determine the frequency of clock
14、for system. The default system clock Fosc = 24.576MHz and CPU clock is Fosc/8 if not specified. The initial CPU clock is Fosc/8 after system wakes up and to be adjusted to desired CPU clock by programming the Port_SystemClock (W). This avoids Flash ROM reading failure when system wakes up.5.3.1.2. 3
15、2768Hz RTCThe Real Time Clock (RTC) is normally used in watch, clock or other time related products. A 2Hz-RTC (1/2 second) function is loaded in SPCE061A. The RTC counts the timing as well as to wake CPU up whenever RTC occurs. Since the RTC is generated each 0.5 seconds, time can be traced by the
16、numbers of RTC occurrence. In addition, SPCE061A supports 32768Hz oscillator in normal mode and auto-power-saving mode. In normal mode, 32768Hz OSC always runs at the highest power consumption. In auto-power-saving mode, however, it runs in normal mode for the first 7.5 seconds and changes back to p
17、ower-saving mode automatically to save powers.5.4. Standby ModeThe SPCE061A also offers a standby mode for low power application needs. To enter standby mode, the desired key wakeup port (IOA 7:0) must be configured to input first. And read the Port_IOA_Latch(R) to latch the IOA state before enterin
18、g the standby mode. Also remember to enable the corresponding interrupt source(s) for wakeup. After that, stop the CPU clock by writing the STOP CLOCK Register (b0b2 of Port_SystemClock (W) to enter standby mode. In such mode, SRAM and I/Os remain in the previous states till CPU being awoken. The wa
19、keup sources in SPCE061A include Port IOA7 - 0 and IRQ1 - IRQ6. After SPCE061A is awoken, the CPU will continue to execute the program. Programmer can also enable or disable the 32768Hz OSC when CPU is in standby mode.5.5. Low Voltage Detection and Low Voltage Reset 5.5.1. Low voltage detection (LVD
20、) There are two LVD levels to be selected: 2.9V, and 3.3V. These levels can be programmed via Port_LVD_Ctrl (W). As an example, suppose LVD is given to 2.9V. When the voltage drops below 2.9V, the b15 of Port_LVD_Ctrl is read as HIGH. In such state, program can be designed to react to this condition
21、. 5.5.2. Low voltage reset In addition to the LVD, the SPCE061A has another important function, Low Voltage Reset (LVR). With the LVR function, a reset signal is generated to reset system when the operating voltage drops below 2.3V for 10 consecutive CPU clock cycles. Without LVR, the CPU becomes un
22、stable and malfunctions when the operating voltage drops below 2.3V. The LVR will reset all functions to the initial operational (stable) states when the voltage drops below 2.3V. A LVR timing diagram is given as follows: 5.6. InterruptThe SPCE061A has 14 interrupt sources, grouped into two types, F
23、IQ (Fast Interrupt Request) and IRQ (Interrupt request). The priority of FIQ is higher than IRQ. FIQ is the high-priority interrupt while IRQ is the low-priority one. An IRQ can be interrupted by a FIQ, but not by another IRQ. A FIQ cannot be interrupted by any other interrupt sources.5.7. I/OTwo I/
24、O ports are built in SPCE061A, PortA and PortB. The PortA is an ordinary I/O with programmable wakeup capability. In addition to the regular IO function, the PortB can also perform some special functions in certain pins. Suppose operating voltage is running at 3.6V (VDD) and VDDIO (power for I/O) op
25、erates from 3.6V (VDD) to 5.5V. In such condition, the I/O pad is capable of operating from 0V through VDDIO. However IOB13 and IOB14 are recommended to operate =3.6V during standby mode, otherwise these two IOs will have current leakage. The following diagram is an I/O schematic.Although data can b
26、e written into the same register through Port_Data and Port_Buffer, they can be read from different places, Buffer (R) and Data (R). The IOA 7:0 is the key wakeup port. To activate key wakeup function, latch data on PORT_IOA_Latch and enable the key wakeup function. Wakeup is triggered when the Port
27、A state is different from at the time latched. In addition to an ordinary I/O port, PortB carries some special functions. A summary of PortB special functions is listed as follows: Refer to the above table, the configuration of IOB2, IOB3, IOB4, and IOB5 involves feedback function in which an OSC fr
28、equency can be obtained from EXT1 (EXT2) by simply adding a RC circuit between IOB2 (IOB3) and IOB4 (IOB5).5.8. Timer / CounterThe SPCE061A provides two 16-bit timers/counters, TimerA and TimerB. The TimerA is called a universal counter. TimerB is a general-purpose counter. The clock source of Timer
29、A comes from the combination of clock source A and clock source B. In TimerB, the clock source is given from source C. When timer overflows, an INT signal is sent to CPU to generate a time-out signal.Initially, write a value of N into a timer and select a desired clock source, timer will start count
30、ing from N, N+1, N+2, . through FFFF. An INT (TimerA/TimerB) signal is generated at the next clock after reaching “FFFF” and the INT signal is transmitted to INT controller for further processing. At the same time, N will be reloaded into timer and start all over again. The clock source A is a high
31、frequency source and clock source B is a low frequency source. The combination of clock source A and B provides a variety of speeds to TimerA. A “1” represents pass signal and not gating. In contrast, “0” indicates deactivating timer. The EXT1 and EXT2 are the external clock sources. Moreover, count
32、er can generate time-out signal for input clock source to a four bits (16 levels) PWM pulse width counter. A variety of clock duration can be generated and exported from IOB8 (APWMO) and IOB9 (BPWMO).The following example is a 3/16-duration cycle. The APWMO waveform is made by selecting a pulse widt
33、h through Port_TimerA_Ctrl (W) 9:6. As a result, each 16 cycles will generate a pulse width defined in control port. These PWM signals can be applied for controlling the speed of motor or other devices.Generally speaking, the clock source A and C are fast clock sources and source B comes from RTC sy
34、stem (32768Hz). Therefore, clock source B can be utilized as a precise counter for time counting, e.g., the 2Hz clock can be used for real time counting.5.8.1. TimebaseTimebase, generated by 32768Hz, is a combination of frequency selections. The outputs of timebase block are named to TMB1 and TMB2.
35、TMB1 is frequency for TimerA (Clock source B). The TMB1 and TMB2 are the sources for Interrupt (IRQ6). Furthermore, timebases generates additional 2Hz to 4096Hz interrupt sources (IRQ4 and IRQ5) for Real-Time-Clock (RTC).5.9. Sleep, Wakeup and Watchdog5.9.1. Wakeup and sleep1) Sleep: After power-on
36、reset, IC starts running until a sleep command occurs. When a sleep command is accepted, IC will turn the system clock (PLL) off. After all, it enters sleep mode.2) Wakeup: CPU waking up from sleep mode requires a wakeup signal to turn the system clock (PLL) on. The IRQ signal makes CPU to complete
37、the wakeup process and initialization. The key wakeup and interrupt sources (IRQ1 - IRQ6) can be used for wakeup sources.5.9.2. WatchdogThe purpose of watchdog is to monitor if the system operates normally. Within a certain period, watchdog must be cleared. If watchdog is not cleared, CPU assumes th
38、e program has been running in an abnormal condition. As a result, the CPU will reset the system to the initial state and start running the program all over again. The watchdog function can be removed by bonding option. In SPCE061A, the clear period is 0.75 seconds. If watchdog is cleared within each
39、 0.75 seconds, the system will not be reset. To clear watchdog, simply write “xxxx xxxx xxxx xx01B” to Port_Watchdog_Clear(W). The content written to Port_Watchdog_Clear(W) for watchdog clearance must be exactly the same as the one illustrated above (xxxx xxxx xxxx xx01B). Other values given to the
40、Port_Watchdog_Clear(W) for watchdog clearance may end up with system reset. The watchdog function remains enabled during standby mode if the 32768Hz is turned on.5.10. ADC (Analog to Digital Converter) / DACThe SPCE061A has eight channels 10-bit ADC (Analog to Digital Converter). The function of an
41、ADC is to convert analog signal to digital signal, e.g. a voltage level into a digital word. The eight channels of ADC can be seven channels of line-in from IOA 6:0 or one channel microphone (MIC) input through amplifier and AGC controller. The MIC amplifier circuit is capable of reducing common mod
42、e noise by transmitting signals through differential MIC Inputs (MICN, MICP). Moreover, an external resistor can be applied to adjust microphone gain and time of AGC operating. The AD needs to select source of line-in before conversion. The ADC is able to choose the external or internal (=AVDD) top
43、reference voltage. If constant voltage source is unavailable, SPCE061A offers a constant voltage 2.0V with 5.0mA driving ability with a capacitor connected.The SPCE061A has two 10-bit D/A with 2.0mA or 3.0mA driving current for audio outputs, DAC1 and DAC2.5.11. Serial Interface I/O (SIO)Serial inte
44、rface I/O offers a one-bit serial interface for communication. This serial interface is capable of transmitting or receiving data via two I/O pins, IOB0 (SCK) and IOB1 (SDA).5.12. UARTUART block provides a full-duplex standard interface that facilitates the communication with other devices. With thi
45、s interface, SPCE can transmit and receive simultaneously. The maximum baud-rate can be up to 115200bps. This function can be accomplished by using PortB and Interrupt (UART IRQ). The Rx and Tx of UART are shared with IOB7 and IOB10. When SPCE061A receives and/or transmits a frame of data, the b7 (R
46、xRDY) and/or b6 (TxRDY) in Port_UART_Command2(R) will be set to “1” and the UART IRQ is activated at the same time.SPCE061A 32K x 16 语音控制器1. 总述SPCE061A 是继nSP系列产品SPCE500A等之后凌阳科技推出的又一个16位结构的微控制器。与SPCE500A不同的是，在存储器资源方面考虑到用户的较少资源的需求以及便于程序调试等功能，SPCE061A里只内嵌32K字的闪存FLASH ROM。较高的处理速度使nSP能够非常容易地、快速地处理复杂的数字信号
47、。因此，与SPCE500A相同，以nSP为核心的SPCE061A微控制器也适用在数字语音识别应用领域。SPCE061A在2.6V3.6V电压范围内的工作速度范围为0.32MHz49.152MHz，较高的工作速度使其应用领域更加拓宽。2K字SRAM和32K字闪存ROM仅占一页存储空间，32位可编程的多功能I/O端口；两个16位定时器/计数器；32768Hz实时时钟；低电压复位/监测功能；8通道10位模-数转换输入功能并具有内置自动增益控制功能的麦克风输入方式；双通道10位DAC方式的音频输出功能。SPCE061A是数字声音和语音识别产品的一种最经济的应用。2. 性能 16位nSP微处理器； 工作
48、电压：VDD为2.63.6V(cpu), VDDH为VDD5.5V(I/O)； CPU时钟：0.32MHz49.152MHz ； 内置2K字SRAM； 内置32K闪存ROM； 可编程音频处理； 晶体振荡器； 系统处于备用状态下(时钟处于停止状态)，耗电小于2A3.6V； 2个16位可编程定时器/计数器(可自动预置初始计数值)； 2个10位DAC(数-模转换)输出通道； 32位通用可编程输入/输出端口； 14个中断源可来自定时器A / B，时基，2个外部时钟源输入，键唤醒； 具备触键唤醒的功能； 使用凌阳音频编码SACM_S240方式(2.4K位/秒)，能容纳210秒的语音数据； 锁相环PLL振
49、荡器提供系统时钟信号； 32768Hz实时时钟； 7通道10位电压模-数转换器(ADC)和单通道声音模-数转换器 声音模-数转换器输入通道内置麦克风放大器和自动增益控制(AGC)功能； 具备串行设备接口； 低电压复位(LVR)功能和低电压监测(LVD)功能； 内置在线仿真板(ICE，In- Circuit Emulator)接口。3. 结构框图SPCE061A的结构如下图3.1所示：图3.14. 应用领域 语音识别类产品 智能语音交互式玩具 高级亦教亦乐类玩具 儿童电子故事书类产品 通用语音合成器类产品 需较长语音持续时间类产品5. 功能描述5.1. CPUSPCE061A配备了凌阳科技开发的最新的16位微处理器nSP。它内含有8个寄存器：4个通用寄存器R1R4，1个程序计数器PC，1个堆栈指针SP，1个基址指针BP和1个段寄存器SR。通用寄存器R3和R4结合形成一个32位寄存器MR，MR可被用作乘法运算和内积运算的目标寄存器。此外，SPCE061A有3个FIQ中断和14个IRQ中断，并且带有一个由指令BR
