第6章锁存器和触发器.ppt

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1、Chapter 6.Integrated Flip-Flops,本章任务（学习内容）,1.用NAND门构成的基本锁(Latch）；2.能解释SR锁(Latch)和D锁(Latch)的区别；3.能区分Latch和Flip-Flop的区别；4.解释SR、D和JK F.F.之间的不同；5.解释边沿和主-从F.F.之间有什么不同；6.F.F.的基本应用；7.几个重要参数；,Flip-Flops classify:SEC.6.1 触发器的分类:,1.按电路结构分类:Basic R-S F.F（Latch）Synchronous R-S F.FMaster-Slave F.FTransparent D-F

2、.F.The pulse Edge-Triggered D F.F.2.按逻辑功能的分类:R-S F.FD-FFJ-K FFT-F.F.（T-F.F）,一.基本R-S触发器的性质:,S,R,特点：有记忆功能（保持功能）,1.NAND gate S-R Latch.,R S Qn Qn+11 1 0 0 状态不变 1 1 1 0 0 1 置1(SET 1)1 1 0 1 0 0 置0(SET 0)1 0 0 0 0 x 状态不定 1 x,S,R,Q,Q,Qn：初始状态,INPUT,OUTPUT,初态,（补）2.S-R（NAND）Latch(锁的特性方程)characteristic equati

3、on,Qn+1,Qn,01,00 01 11 10,SR,X 1X 1,1 1,(S),RQn,Qn+1=(S)+RQn S+RQn S R 1（约束条件）,SR Latch.波形描述,SDRDQnQn+1,状态不定,1,1,0,1,1,1,1,0,0,0,【例6.9.1.】用VHDL语言描述基本的S-R锁。解：LIBRARY ieee;USE ieee.std_logic_1164.ALL;ENTITY SR_latch1 IS port(S,R：in std _logic;Q,Q：buffer std _logic);-输出为缓冲方式 End Entity SR_latch1;Archit

4、ecture dataflow of SR_latch1 IS Begin Q=1when R=0else 0when S=0else Q;Q=1when S=0else 0when R=0elseQ;End Architecture dataflow；,2.NOR R-S Flip-Flop,Sd Rd Qn Q n+1 0 0 0 0 0 0 1 1 1 0 0 1 1 1 0 1 0 0 1 0 1 1 0 x 1 x,Sec 6.2 同步式R-S触发器,Synchronous R-S Flip-Flop,1.The gate Set-Reset Flip-Flop,Characteri

5、stic Equation:Qn+1=S+RQn RS=0,Q,Q,1,2,思路：引入 cp（clock pulse）做控制信号,cp,set,Reset,2.The gate Set-Reset Flip-Flop（Latch）true table,Cp SET RESET Qn Qn+1 0 x x Q Q 1 0 0 Q Q 1 0 1 1 0 1 1 0 0 1 1 1 1 1 1,Unchangedstate,Unused state,.Set-Reset Flip-Flop Characteristic equation,Cp SET RESET Q n Qn+1 1 0 0 0

6、0 1 1 1 0 1 0 0 1 0 1 1 0 0 1 1 1 1 1 1 0 1 1 1,Q-Unchanged,0,1,Unused,1,2,3,4,.Synchronous SR F.F.Characteristic Equation,Qn,SR,00 01 11 10,01,S,R Qn,Qn+1=S+RQn；S R=0；（约束条件）,补,(4).State Transition diagram,0,1,R=0,S=1,S=0,R=1,R=0S=X,S=0R=X,1,2,3,4,激励表,Qn Q n1,S R,0 00 11 01 1,0 00 11 01 1,0 x1 00 1x

7、 0,补,通常很容易将基本的S-R锁和触发器概念相混淆，下面给出明确的定义。基本S-R触发器又叫门锁电路，它是对电平灵敏的记忆元件，是基于交叉耦合的门组成的。触发器指的是时钟脉冲或边沿触发的记忆元件。用VHDL建模时，可以有多种方法，下面仅讨论两种设计方法。【例6.9.2.】基本S-R触发器设计。解：Library ieee;Use ieee.std_logic_1164.All;Entity SR_latch2 IS Port(S,R：in std_logic；-logic为初始值 Q，Q：out std_logic)；End Entity SR_latch2;,Architecture b

8、ehavior of SR_latch2 IS Begin p0：process(R,S)IS Begin Case std_logic_vector（R,S）is when“00”=Q Q Q Null；End Case;End Process P0;End Architecture behavior;,第二种设计方法首先在实体说明中说明了Q和Q为输出方式。因为在模型的内部不读它们。如果S或R有一个为零，或两者全为零，Q和Q只是被反复求值，如果S和R两者全为1，输出保持不变。注意在描述行为的结构体中，case语句是必要的，case语句的一般格式为：Case 条件表达式 is When 条件表

9、达式的值=顺序处理语句；End case；Case语句是无序的，所有表达式的值都并行处理。Case语句中的条件表达式的值必须全部表述出来,且不能重复。不能全部表述的条件表达式的值用others表示。,Chapter 4.IC.F.F.第一讲小结,基本SR Latch逻辑电路图,状态转换表,特性（征）方程,状态转换图,状态激励表,波形图描述,分析,K-图化简,图6.2.1.S-R锁电路及符号,SR,RDSD,QQ,SDRD,QQ,1,1,RDSD,QQ,（a）,（b）,（c）,SR,SDRD,QQ,（d）,（a）.NOR锁电路符号;（b）.NOR门组成的S-R锁电路;（c）.NAND锁电路符号;

10、（d）.NAND门组成的S-R锁电路;,表6.2.1 S-R锁电路功能表,NAND 锁,NOR 锁,Qn,Qn,Qn+1,Qn+1,SD RD,SD RD,0 00 00 10 11 01 01 11 1,1 1 1 1 0 10 11 01 00 00 0,01010101,01010101,01110011,01110000,图6.3.1.有引导门的S-R锁,S,R,Enable,G1,G2,Q,Q,S,R,图6.3.2（a）Enable作控制信号,EN,S,R,Q,图6.3.2（b）Enable作为同步信号,CLK=EN,S,R,Q,Sec.6.3 D-F.F.,The transpar

11、ent data flip-flop,1.Gated D-latch,Graphical symbol,Data,s,R,D QClk Q,思路：禁止出现S=R=1，使 Q（状态不定）,Q,Q,CLK,D,R,Enable,G1,G2,Q,Q,S,R,D QEn Q,（a）（b)图6.3.5（a）.门控D锁（b）.门控D-锁的电路符号,门控D锁和D触发器,2.The transparent D-f.f.Characteristic,Clk D Qn Qn+1 0 0 0 0 1 0 1 0 1 1 1 1,D-f.f.state Transition diagram,0,1,D=1,D=0,D

12、=0,D=1,Synchronous D F.F.Characteristic Equation,01,0 1,Qn,D,D,Qn+1=D,Qn+1,(3).D-F.F.State Transition diagram,1,0,D=1,D=1,D=0,D=0,3.强调Enable行为的D锁设计 如果D锁存器要求强调在enable信号控制下工作，D的输入才被传送到输出。图6.9.5中D表示出它的输入，D取决于控制信号 Enable（C）。下面是描述D锁的行为模型。,【例6.9.3】.用进程语句描述一个D锁的行为。-d_latch_vhdl.vhd-D latch with activeHIGH

13、levelsensitive enable ENTITY d_latch_vhdl IS PORT(d,ena：IN BIT；q：OUT BIT）；END d_latch_vhdl；ARCHITECTURE act OF d_latch_vhdl IS BEGIN PROCESS(d,ena)BEGIN IF(ena=1)THEN Q=d；End IF；End PROCESS End act；,图6.9.3 d_latch_vhdl的仿真波形图,【例6.9.4】用例示元件程序包设计一位D锁存器。-latch_primitive.vhd-D latch with active-HIGH leve

14、l sensitive enable LIBRARY ieee；要求std_logic类型；USE ieee.std_logic_1164.ALL；LIBRARY altera；要使用的锁元件 USE altera.maxplus2.ALL；ENTITY latch_primitive IS PORT(d_in，enable：IN STD_LOGIC；q_out：OUT_ LOGIC)；END latch_primitive；ARCHITECTURE act OF latch_primitive IS BEGIN-Instantiate act latch from a primitive l

15、atch_prim：latch PORT MAP(d=d_in，ena=enable，q=q_out)；END act；,2.用生成语句产生4_位锁存器【例6.9.7】使用生成（GENERATE）语句设计4_位锁存器。-latch_primitive.vhd-D latch with active-HIGH level sensitive enable LIBRARY ieee；USE ieee.std_logic_1164.ALL；LIBRARY altera；USE altera.Maxplus2.ALL；ENTITY latch4_primitive IS PORT(d_in：IN ST

16、D_LOGIC_VECTOR(3 downto 0)；enable：IN STD_LOGIC；q_out：OUT STD_LOGIC_VECTOR(3 downto 0)；END latch4_ primitive ARCHITECTURE act OF latch4_ primitive IS BEGIN-Instantiate a latch primitive from maxplus2 package latch4：G1：FOR i IN 3 downto 0 GENERATE latch_ primitive：latch PORT MAP(d=d_in（i），ena=enable，q

17、=q_out（i）)；END GENERATE G1；END act；,Sec.6.4.主-从式触发器,The Master-Slave F.F,1.The Master-Slave D-F.F.,D,CL K,QS,QS,QM,QM,Master-F.F.,Slave-F.F.,1,0,0,1,(1).Negative edge triggered Master-slave D-F.F.Timing waveform diagram,master-clk,Slave-clk,DQm,Qs,1,2,3,4,M-dir-on,M-tr.S-close,S-dir-on,M-tr.S-close,

18、干扰信号,Negative edge-triggered Master-Slave D-F.F.Simplified configuration,Q,QS,Sec.6.5.主从结构RS触发器,6.主从结构RS触发器（a）电路结构（b）图形符号,返回,Preset,CLR,Master-Slave S-R F.F.Truth Table,cp,Qn,Qn+1,S R,x x0 00 01 01 00 10 11 11 1,x 0 1 0 1 0 1 0 1,0 1 1 1 0 0 1 1,x,Qn,QnUn-changed,QnSet-1,QnSet-0,QnUn-used,Timing wav

19、eform diagrams,图4.2.9 例4.2.8 的电压波形图,返回,Negative edge-triggeredMaster-slave R-S F.F.,PLD integration p.398,MasterF.F空翻.,slaverF.F波形图.,1.注意主F.F.和从F.F.翻转的时刻；2.解释第个时钟脉冲产生空翻。,7.Positive edge triggered master-slave D-F.F.,Clear,preset,Q,Q,触发器异步置位和复位的完整程序文件如下：LIBRARY ieee；USE ieee.std_logic_1164.all；ENTITY

20、 d_ff_r IS Port(D,Clock，Reset：in std_logic；Q：out std_logic)；End ENTITY d_ff_r；Architecture behavioural of d_ff_r IS BEGIN p0：PROCESS（Clock，Reset）IS BEGIN IF（Reset=0）then Q=0；elsif（clock event and clk=1）then-等待clk激活，clk是clk的次态；Q=D；-当clk=1条件成立时.End IF；END PROCESS p0；End Architecture behavioural；,Sec6.

21、6.The J-K master-slave F.F.,The J-K master-slave F.F.,The way of thinking:,DT,Digital-2.p.50,DF.F.JK.FF.JK.FF.TF.F.,Master-Slave JK F.F.,Preset,Clear,J,K,CLK,Q,Q,Master-Slave JK F.F.Truth Table,Preset clear J K clk Qn Qn+1 0 1 X X X 1 0 1 0 X X X 0 1 0 0 X X X 1 1 Unsed state 1 1 0 1 x 0 1 1 1 0 x 1

22、 1 1 0 0 Q Q Unchanged 1 1 1 1 Toggle,JKF.F.特征方程：Qn+1=J Qn+K Qn,Toggle,Q,JK F.F.,Qn,JK,00 01 11 10,01,JQn,KQn,Qn+1,Qn+1=JQ+KQ,Output waveforms for a J-K f.f.,CLK,1 2 3 4 5 6 7 8 9,1 1,1 0 0 1 0 0,J,K,Clear,preset,Q,Q,0,0,1,0,Master-slave J-K F.F.State conversion diagram,0,1,J=1 K=X,J=X K=1,J=0K=X,J=

23、XK=0,JK触发器和T触发器的设计也能用上述的方法把状态看成信号或变量来处理。【例6.9.13】J_K.触发器的设计。Library ieee;Use ieee.std_logic_1164.All;Entity jk_ff IS port(j,k,CLK,Reset：in std_logic;Q1,Q2：out std_logic);End Entity jk_ff;Architecture sig OF jk_ff IS Signal state：std_logic Begin p0：Process（clk,Reset）IS Begin If（Reset=0）thenstate=0；El

24、sif rising_edge（clk）then Case std_logic_vector（j,k）ISWhen“11”=state=not state；,When“10”=state=1；When“01”=state=0；When Others=Null；End Case;End If;End Process p0;Q1=state;Q2=not state；End Architecture sig；,【例6.9.14】T.触发器设计Library ieee;USE ieee.std_logic_1164.All;Entity T_FF IS port(T,CLK,Reset：in std

25、_logic;Q1,Q2：out std_logic);End Entity T_FF;Architecture var of T_FF Is Begin p0：Process（clk,Reset）IS Variable State：std_logic;Begin If（Reset0）Then state：=0;Elsif rising_edge（clk）Then If T=1 then state：=not state;End If;End If;Q1=state;Q2=not state；End Process p0;End Architecture var;,Chapter 4.IC.F

26、.F.第2讲小结,基本SRLatch同步S RLatch,DLatch,主从式DF.F.,Toggling,主从式RS F.F.,主从式JK F.F.,（状态不定）,RSCLK=1,空翻,Qn R Qn+1 S 引反馈线,主从式JK F.F.,仍然：存在一次翻转现象,D-F.F.防止空翻的措施引反馈线,D,CLK,Qm,Qm,Qn,反馈线,Qn,Toggling a master-Slave D-F.F.timing diagram,clk,1,2,3,4,D,Qm,Qm,Qs,Qs,0,0,0,t CLK,T MS=2 t CLK,Sec4.6.边沿式触发器,The principle of

27、 edge Triggering,Pulse edgedetector,S,R,CLK,Delay,CLK,Q,Q,A type of pulse positive transition detector,This gate is enabled.,The principle of edge Triggering,Pulse edgedetector,S=1,R=0,CLK,Delay,CLK,Q,Q,This spike sets f.f.=1,This gate is enable.,1,0,0,1,Digital-2.p.67.,The edge triggered D-F.F.,CLK

28、,D,Q,Q,S,R,Digital-2.p.68,A positive edge-triggered D-F.F.formed with an S-R F.F.and an inverter,【例6.9.9.】用VHDL描述上升沿触发的D触发器。LIBRARY ieee;USE ieee.std_logic_1164.ALL;ENTITY d_ff IS PORT(d,clk：IN std_logic;Q：OUT std_logic);END ENTITY d_ff；ARCHITECTURE behavioural OF d_ff IS BEGIN p0：PROCESS IS BEGIN W

29、AIT UNTIL(CLK=1);Q=D；END PROCESS p0；END ARCHITECTURE behavioral；,【例6.9.10】上升沿触发的D触发器设计。解：LIBRARY ieee;USE ieee.std_logic_1164.ALL;ENTITY d_ff IS PORT(d,clk：IN std_logic;Q：OUT std_logic);END ENTITY d_ff；ARCHITECTURE alternative OF d_ff IS BEGIN p0：PROCESS（CLK）IS BEGIN IF(CLK=1)THEN Q=D；END IF；END PRO

30、CESS p0；END ARCHITECTURE alternative；本例中只要clock改变状态，process将反复求值。,【例6.9.11】上升沿触发的D触发器设计。LIBRARY ieee;USE ieee.std_logic_1164.ALL;ENTITY d_ff IS PORT(d,clk：IN std_logic;Q：OUT std_logic);END ENTITY d_ff；ARCHITECTURE equivalent OF d_ff IS BEGIN p0:PROCESS IS BEGIN IF(CLK=1)THEN Q=D；END IF;wait on(CLK=1

31、);END PROCESS p0；END ARCHITECTURE equivalent；有灵敏度表的进程和有wait on语句（在进程结束时）的进程是等效的。wait语句的wait on形式可以引起process执行暂停，直到信号列表或信号发生变化之前。,【例6.9.12】用VHDL描述下跳沿触发的D_触发器。LIBRARY ieee;USE ieee.std_logic_1164.ALL;ENTITY d_ff IS PORT(d,clk：IN std_logic;Q：OUT std_logic);END ENTITY d_ff；Architecture neg_edge OF d_ff

32、IS Begin p0：PROCESS IS Begin Wait Until(clk=0);Q=D；End Process P0；End Architecture neg_edge；,A positive edge Triggering J-K F.F.,Pulse edgedetector,J,K,CLK,Delay,CLK,Q,Q,Slide 37,The principle of edge Triggering,Pulse edgedetector,J,K,CLK,Delay,CLK,Q,Q,Digital-2 p.68.,Truth table for a positive edge

33、-triggered J-K F.F.,Inputs Outputs Comments J K CLK Q Q 0 0 Qo Qo no change 0 1 0 1 reset 0 1 0 1 0 set 1 1 1 Qo Qo toggle,思考题：J-K F.F.Applications:,The nonoverlapping clock,1,Draw the logic diagram and waveforms for a nonoverlapping clock and the waveforms for cp1 and cp2using a 74Ls76 and a 74Ls02

34、 IC.,Sec4.7.F.F.Logic function conversion,1.D-F.F.to J-K F.F.2.D-F.F.to T-F.F.3.J-K F.F.to D-F.F.4.D-F.F.to S-R F.F.,F.F.Logic function conversion Lecture-2.p.61,1.D-F.F.to J-K F.F.,QQ,K,J,Qn+1=JQn+KQn=(JQn+KQn)=(（JQ）（KQ）)Qn+1=D=(（JQ）（KQ）),2.D-F.F.to T-F.F.,CLK,Qn+1=JQn+KQnQn+1=TQn+TQn=TQnD=TQn,3.J-

35、K F.F.to D-F.F.,4.D-F.F.to S-R F.F.,CP,Q,R,S,FLIP-FLOP Summary:,1.Basic S-R F.F.The properties of the S-R F.F.2.A five analysis methods.State Transition Table;Next state karnaugh-map;State Transition diagram;Characteristic equation;Timing waveforms;Defect:State uncertain,3.Synchronous S-R F.F.(The g

36、ated S-R F.F.)Synchronoued(CLK);Defect:The state uncertain 4.DF.F.DLatched,transparten.When cp=1,The F.F.appears multiplex transition;,The Master-Slave D-F.F.,.The Master F.F.(D-F.F.)+Slave(S-R F.F.);.Slave F.F.The State not Uncertain;.The Master f.f.appears multiplex transition;Toggling a MasterSla

37、ve DF.F.NOT appears multiplex transition;,The Master-Slave J-K F.F.,The type of F.F.can be wired or programmed to do the job of any type of F.F.The Q AND Q outputs are wired back to K and J gates respectively.This will allow the flip-flop to toggle when the J and K inputs are 1s.The J and K inputs a

38、re used to steer the outputs.There are 2 inputs,called preset and clear,which force the Q output to 1 and 0,respectively,when they are brought Low.Not uncertain states.,Three different types of storage elements that are driven by the same data and clock inputs.To accentuate the differences between t

39、hese storage elements,the D input changes its values more than once during each half of the clock cycle.Try to draw the timing waveforms of the logical circuit.,D,CLK,D,D,D,CLK,CLK,CLK,Q a,Q b,Q c,Chapter Summary:,Level triggered F.F:Basic Latch Gated S-R Latch Gated D-latch Master-Slave D-Latch Tog

40、gling Master Slave D latch Master slave J-K F.F.Edge Triggered F.F:The edge triggered D-f.f.The edge triggered J-K f.f.Maintain-prevention D-F.F.,Sec4.6.The FLIPFlop of edge Triggering,The principle of edge Triggering,Pulse edgedetector,S,R,CLK,Delay,CLK,Q,Q,A type of pulse positive transition detec

41、tor,This gate is enabled.,The principle of edge Triggering,Pulse edgedetector,S=1,R=0,CLK,Delay,CLK,Q,Q,This spike sets f.f.=1,This gate is enable.,1,0,0,1,Digital-2.p.67.,A positive-edge-triggered D Flip-flop,With VHDL Design p.343,p1,p2,p3,p4,A positive-edge-triggered D Flip-flop,With VHDL Design

42、p.347,Clear,preset,Edge-triggered J-K f.f.equivalent function using an edge-triggered D f.f.,D,CLK,J,K,J,K,Q,Q,Symbol,Digital Design-p.547,第五章 作 业,5.1 5.235.2 5.245.13 5.255.14 5.16.5.17 5.18,Toggling A Master-Slave D-F.F.,A way of thinking:,Digital-2.p.49,Sec.6.6.主从式JK F.F.The J-K master-slave F.F.

43、,The way of thinking:由输出向对方引反馈线,DT,Digital-2.p.50,1,2,Q,Q,1,2,反馈线使引导门输入不会出现J=K=1的状态不定情况,Master-Slave JK F.F.,Preset,Clear,J,K,CLK,Q,Q,1,2,3,4,Master-Slave JK F.F.Truth Table,Preset clear J K clk Qn Qn+1 0 1 X X X X 1 1 0 X X X X 0 0 0 X X X 1 1 Unsed state 1 1 0 1 X 0 1 1 1 0 X 1 1 1 0 0 X Q Q Unchanged 1 1 1 1 Q Q,Qn+1=J Qn+K Qn,Toggle,JK F.F.特性表示在卡诺图中,Qn,JK,00 01 11 10,01,JQn,KQn,Qn+1,Qn+1=JQn+kQn,Output waveforms for a J-K f.f.,CLK,1 2 3 4 5 6 7 8 9,1 1,1 0 0 1 0 0,J,K,Clear,Preset,Q,Q,0,0,1,0,主从式JK F.F.状态转换图Master-slave J-K F.F.State conversion diagram,0,1,J=1 K=X,J=X K=1,J=0K=X,J=XK=0,