《QuartusII时序约束方法.ppt》由会员分享，可在线阅读，更多相关《QuartusII时序约束方法.ppt（223页珍藏版）》请在三一办公上搜索。
1、Quartus II Software Design Series:Timing Analysis,常见术语的中文翻译,Tsetup:建立时间Thold：保持时间Skew：传输时差,时钟歪斜Slack：余量Fmax：最大频率Input maximum delay：输入最大延时Input minimum delay：输入最小延时Output maximum delay：输出最大延时Output minimum delay：输出最小延时Max delay：最大延时Min Delay：最小延时Recovery time：恢复时间Removal time：移去时间Jitter：抖动,TimeQuest
2、 Agenda,Introduction to TimeQuestTimeQuest terminology reviewUsing TimeQuestExample Application,TimeQuest Timing Analyzer,New timing engine in Quartus IIProvide timing analysis solution meeting requirements of all usersFPGA design backgroundASIC design backgroundEasy-to-use interfaceStandard reporti
3、ng&constraint terminology Scripting emphasis,TimeQuest Timing Analyzer(cont.),More accurate analysisrise/fall delaysSDC SupportMore advanced&standardized constraint methodologyEasily supports more complex designs and analysisComplex clocking schemesSource-synchronous designs,Validating Performance w
4、ith the TimeQuest Static Timing Analyzer,TimeQuest Terminology Review,TimeQuest Terminology Review,Launch&latch edgesArrival time vs.required timeSetup&hold analysisSlackSDC terminology,Path&Analysis Types,Three types of Paths:Clock PathsData PathAsynchronous Paths*,Clock Paths,Async Path,Data Path,
5、Async Path,Two types of Analysis:Synchronous clock&data pathsAsynchronous*clock&async paths,*Asynchronous refers to signals feeding the asynchronous control ports of the registers,Setup&Hold,Setup:The minimum time data signal must be stableBEFORE clock edgeHold:The minimum time data signal must be s
6、tableAFTER clock edge,CLK,DATA,Together,the setup time and hold time form a Data Required Window,the time around a clock edge in which data must be stable.,Launch&Latch Edges,CLK,Launch Edge,Latch Edge,Data Valid,DATA,Launch Edge:the edge which“launches”the data from source registerLatch Edge:the ed
7、ge which“latches”the data at destination register(with respect to the launch edge,typically 1 cycle),Launch&Latch Edges,Launch Edge:Clock edge that activates the source register in a register-to-register pathLatch Edge:Clock edge that activates the destination register,CLKA,CLKB,CLKA,CLKB,The relati
8、onship between the edges is derived from the user-defined clock settings,Data Arrival Time,The time for data to arrive at a registers D input,Data Arrival Time=launch edge+Tclk1+Tco+Tdata,LaunchEdge,Clock Arrival Time,The time for clock to arrive at a registers clock input,Clock Arrival Time=latch e
9、dge+Tclk2,LatchEdge,Data Required Time-Setup,Time signal must arrive at destination register to be properly sampled,Data Required Time=Clock Arrival Time Tsu,LatchEdge,Data Required Time-Hold,Data Required Time=Clock Arrival Time+Th,LatchEdge,Earliest time signal can arrive at destination register a
10、nd not interfere with data sampled on previous clock edge,Slack,Setup Slack=Setup Required Time Data Arrival TimeHold Slack=Data Arrival Time Hold Required TimeSlack must be positive to ensure proper operationEquations work for internal and I/O paths,Why is this important?,Quartus reports timing usi
11、ng this terminologyNo need to memorize!,Input Maximum Delay,Maximum Delay from External Device to Altera I/ORepresents External Device tco+PCB Delay-PCB Clock SkewConstrains Registered Input Path(tsu),A,tco,tsu,Altera Device,External Device,PCB Delay,tsuA tCLK Input Maximum Delay,Input Maximum Delay
12、,tsuA,CLK,CLK,Input Minimum Delay,Minimum Delay from External Device to Altera I/ORepresents External Device tco+PCB Delay-PCB Clock SkewConstrains Registered Input Path(th),A,tco,th,Altera Device,External Device,PCB Delay,thA Input Minimum Delay,Input Minimum Delay,thA,CLK,CLK,Output Maximum Delay,
13、Maximum Delay from Altera I/O to External DeviceRepresents External Device tsu+PCB Delay-PCB Clock SkewConstrains Registered Output Path(Max.tco),B,tco,tsu,Altera Device,External Device,PCB Delay,tcoB tCLK-Output Maximum Delay,tco,Output Maximum Delay,CLK,CLK,Output Minimum Delay,Minimum Delay from
14、Altera I/O to External DeviceRepresents External Device th-PCB Board DelayConstrains Registered Output Path(Min.tco),B,tco,th,Altera Device,External Device,Board Delay,tcoB Output Minimum Delay,tco,Output Minimum Delay,CLK,CLK,SDC Terminology Review,SDC Netlist Example,Sample Pin Names:ina|comboutin
15、rega|dataininrega|clkinrega|regoutab|comboutab|datac,combout,datain,clk,datac,datad,inclk0,regout,outclk,combout,datain,Sample Net Names:inacomboutabclkclkctrlinrega,cell=atom/wysiwyg,pin=oterm,pin=iterm,port=I/O,net,cell,Quartus II Software Design Series:Timing Analysis,Timing Analysis&Settings,How
16、 does timing verification work?,Every device path in design must be analyzed with respect to timing specifications/requirementsCatch timing-related errors faster and easier than gate-level simulation&board testingDesigner must enter timing requirements&exceptionsUsed to guide fitter during placement
17、&routingUsed to compare against actual results,IN,CLK,OUT,combinational delays,CLR,Timing Analysis Agenda,TimeQuest basicsTiming analysis basicsTiming reportsTiming constraintsExample applications,TimeQuest Timing Analyzer,Timing engine in Quartus II softwareProvides timing analysis solution for all
18、 levels of experienceFeaturesSynopsys Design Constraints(SDC)supportStandardized constraint methodologyEasy-to-use interfaceConstraint entryStandard reportingScripting emphasisPresentation focuses on using GUI,Opening TimeQuest,Toolbar buttonTools menuStand-alone modequartus_stawCommand line,TimeQue
19、st GUI,Report Pane,Tasks Pane,Console Pane,View Pane,Menu access to all TimeQuest features,Tasks Pane,Provides quick access to common operationsCommand executionReport generationExecutes most commands with default settingsUse menus for non-default settings,Double-click to execute any command,Report
20、Pane,Displays list of generated reports currently available for viewingReports generated by Tasks paneReports generated using report commands,Highlight report to see detail in View window,Timing Summary Table,View Pane,Main viewing area that displays report table contents&graphical results,Timing Hi
21、stogram,Path Slack Report,Viewing Multiple Reports,Click&drag+sign to divide view pane into multiple windows,Viewing Multiple Reports Example,View pane split into two windows,Highlight window,then highlight report in Reports pane you would like to appear there,Drag bars to edges to remove splits,Use
22、 Target Pane button to force a selected report to appear in a pane,Console pane,Allows direct entry and execution of SDC&Tcl commandsDisplays equivalent of command executed by GUIDisplays TimeQuest output messagesHistory tab records all executed SDC&Tcl commandsCopy&paste to create scripts or SDC fi
23、les,SDC File Editor=Quartus II Text Editor,Use Quartus II editor to create and/or edit SDCSDC editing unique features(for.sdc files)Access to GUI dialog boxes for constraint entry(Edit Insert Constraint)Syntax coloringTooltip syntax help,TimeQuest File menu New/Open SDC FileQuartus II File menu New
24、Other Files tab,Place cursor over command to see tooltip,SDC File Editor(cont.),Construct an SDC file using TimeQuest graphical constraint creation tools,Basic Steps to Using TimeQuest,Generate timing netlistEnter SDC constraintsCreate and/or read in SDC file(recommended method)orConstrain design di
25、rectly in consoleUpdate timing netlistGenerate timing reportsSave timing constraints(optional),1)Generate Timing Netlist,Creates timing netlist(path database)based on compilation results Post-synthesis(mapping)or post-fitWorst-case(slow),best-case(fast)timing models,or set operating conditions(neede
26、d for Stratix III and Cyclone III devices only)To execute:,Netlist menu,Tasks pane,Tcl equivalent of command,Tcl:create_timing_netlist,2a)Create and/or Read in SDC File,Create SDC file using SDC file editorRead in constraints&exceptions from existing SDC fileSkip if no SDC fileExecutionRead SDC File
27、(Tasks pane or Constraints menu)File precedence(if no filename specified)Files specifically added to Quartus II project.sdc(if it exists),Tcl:read_sdc,2b)Constrain Directly in Console,Add new constraints directlyNot automatically added to SDC fileUse GUI or Console paneNot needed if all constraints
28、in SDC fileRecommend using SDC file(step 2a)instead to ease management and storage of constraintsExample constraints(described in detail later)create_clockcreate_generated_clockset_input_delayset_output_delay,Using GUI to Enter Constraints Directly,Most common constraints can be accessed from the Co
29、nstraints menuSame as Edit menu Insert Constraints in SDC file editorUse if unfamiliar with SDC syntax,Constraints menu,Constraining,User MUST enter constraints for all paths to fully analyze designTimeQuest only performs slack analysis on constrained design pathsRecommendation:Constrain all paths(c
30、locks&I/O)Not as difficult a task as it may soundWildcardsSingle,generalized constraints cover many paths,even all paths in an entire clock domain,3)Update Timing Netlist,Apply SDC constraints/exceptions to current timing netlistGenerates warningsUndefined clocksPartially defined I/O delaysCombinato
31、rial loopsUpdate timing netlist after adding any new constraintExecutionUpdate Timing Netlist(Tasks pane or Netlist menu),Tcl:update_timing_netlist,4)Generate Timing Reports,Verify timing requirements and locate violationsCheck for fully constrained design or ignored timing constraintsTwo methodsTas
32、ks paneAutomatically creates/updates netlist&reads default SDC file if neededReports menuMust have valid netlist to accessTasks pane or Reports menu,Double-click on individual report,“Out of Date”Reports,Adding new constraints interactively in console causes current reports to be“out of date”Update
33、timing netlist®enerate reports(report right-click menu)No such warning when using SDC file,Reset Design Command,Located in Tasks paneFlushes all timing constraints from current timing netlistFunctional Tcl equivalent:delete_timing_netlist command followed by create_timing_netlistUses“Re-starting”
34、timing analysis on same timing netlist applying different constraints or SDC fileStarting analysis over if results seem to be unexpected,5)Save Timing Constraints(Optional),write_sdc commandSaves all constraints&exceptions applied to current netlist into SDC fileUse if constraints added during TimeQ
35、uest session in console instead of SDC fileNotesSDC files generated by TimeQuest only if requestedUse-expand option(not in GUI)to convert Altera-specific SDC commands into standard SDCRun report_sdc command(console,Tasks pane,or Report menu)to see what will get written to SDC file,Basic Steps to Usi
36、ng TimeQuest(Review),Generate timing netlistEnter SDC constraintsCreate and/or read in SDC file(recommended method)orConstrain design directly in consoleUpdate timing netlistGenerate timing reportsSave timing constraints(optional),Using TimeQuest in Quartus II Flow,Enable TimeQuest in Quartus II pro
37、ject,Synthesize Quartus II project,Use TimeQuest to specify timing requirements,Verify timing in TimeQuest,Perform full compilation(run Fitter),Follow TimeQuest flowUse-post_map argument for synthesis(mapping)only netlistIf design already fully compiled,choose-post_fit(default)Tasks list command def
38、aults to post-fit,so must use Netlist menu in GUIZero IC delays auto-enabled with Post-mapAssumes no interconnect delays to determine if it will be possible to meet timing,Timing Requirements:Create Post-Map Netlist,Timing Requirements:Enter Constraints,Enter constraints via Constraints menu or Cons
39、ole paneConstraints menu available in main TimeQuest window and in SDC File Editor,Using TimeQuest in Quartus II Flow,Enable TimeQuest in Quartus II project,Synthesize Quartus II project,Use TimeQuest to specify timing requirements,Verify timing in TimeQuest,Perform Full Compilation(run Fitter),Enab
40、ling TimeQuest in Quartus II,Tells Quartus II to use SDC constraints during fittingFile order precedenceAny SDC files manually added to Quartus II project(in order).SDC,Enabling TimeQuest in Quartus II Software,Notes:Arria GX only supports Timequest.TimeQuest is enabled by default for new Stratix II
41、I and Cyclone III designs.,SDC constraints are not stored in QSFTimeQuest can use script to convert QSF timing assignments to SDC Constraints menuDone automatically if no SDC file exists when first opening TimeQuestSee Quartus II Handbook Chapter,“Switching to the TimeQuest Timing Analyzer”for detai
42、lsDifferences between Classic Timing Analyzer and TimeQuestDetails on conversion utilityOnline training also availableSwitching to the TimeQuest Timing Analyzer,Quartus Settings File(QSF),Using TimeQuest in Quartus II Flow,Enable TimeQuest in Quartus II project,Synthesize Quartus II project,Use Time
43、Quest to specify timing requirements,Verify timing in TimeQuest,Perform full compilation(run Fitter),Verifying Timing Requirements,View TimeQuest summary information directly in Quartus II Compilation ReportOpen TimeQuest for more thorough analysisFollow TimeQuest flowRun TimeQuest easy-to-use repor
44、ting capabilities(Tasks pane)Many different reporting options available Place Tcl reporting commands into script fileEasy repetition,TimeQuest Summary Reports,SDC files used during fittingClocks generatedTiming violationsUnconstrained paths,3rd-Party Timing Analysis Tool Support,SynopsysPrimeTimeMen
45、tor GraphicsTAU,Timing Analysis Agenda,TimeQuest basicsTiming analysis basicsTiming reportsTiming constraintsExample applications,Timing Analysis Basics,Launch vs.latch edgesSetup&hold timesData&clock arrival timeData required timeSetup&hold slack analysisI/O analysisRecovery&removalTiming models,Pa
46、th&Analysis Types,Three types of Paths:Clock PathsData PathAsynchronous Paths*,Clock Paths,Async Path,Data Path,Async Path,Two types of Analysis:Synchronous clock&data pathsAsynchronous*clock&async paths,*Asynchronous refers to signals feeding the asynchronous control ports of the registers,Launch&L
47、atch Edges,CLK,Launch Edge,Latch Edge,Data Valid,DATA,Launch Edge:the edge which“launches”the data from source registerLatch Edge:the edge which“latches”the data at destination register(with respect to the launch edge,typically 1 cycle),Setup&Hold,Setup:The minimum time data signal must be stableBEF
48、ORE clock edgeHold:The minimum time data signal must be stableAFTER clock edge,CLK,DATA,Together,the setup time and hold time form a Data Required Window,the time around a clock edge in which data must be stable.,Setup Slack(contd),Positive slackTiming requirement metNegative slackTiming requirement
49、 not met,Setup Slack=Data Required Time Data Arrival Time,Hold Slack(contd),Positive slackTiming requirement metNegative slackTiming requirement not met,Hold Slack=Data Arrival Time Data Required Time,FPGA/CPLD or ASSP,ASSP or FPGA/CPLD,I/O Analysis,Analyzing I/O performance in a synchronous design
50、uses the same slack equationsMust include external device&PCB timing parameters,CL*,Tdata,Tclk1,Tclk2,OSC,Data Arrival Path,Data Arrival Path,Data Required Path,*Represents delay due to capacitive loading,Recovery&Removal,Recovery:The minimum time an asynchronous signal mustbe stable BEFORE clock ed
