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1、1,Compact modeling with VerilogA,Damien QuerliozInstitut dElectronique Fondamentale,Univ.Paris-Sud,CNRS,Orsay,2,Outline,What VerilogA isTwo simple examples=,+and=How it worksUnderstanding automatic derivativesHazards of VerilogA,3,Hardware DESCRIPTION languages,Verilog:digital systemsCan be syntheti
2、zed if low-level codeVerilogA:analog equationsAppropriate for compact modelsVerilogAMS:can mix analog and digital inputs/outputsAllows mixed signal simulation,4,Verilog vs.VHDL,2 competitors:VHDL and VHDL-AMS/Verilog and VerilogA(MS)VHDL more rigorous,Verilog simplerFor digital:USA-Verilog,Europe-VH
3、DLFor analog and mixed signal:USA-VerilogA(MS),Europe-DEPENDS,5,VerilogA vs.C,Compact models used to be written in CNeed to be rewritten for different simualtorsNeed to compute derivatievs by hand Need to write different code for DC,AC,tran analysis BUT you understand performance better BUT VerilogA
4、 can often be as fast as C today,6,A super simple example,include disciplines.vamsmodule R(p,n);electrical p,n;parameter real R=50.0;analog begin V(p,n)+R*I(p,n);endendmodule,Could as well be I(p,n)+V(p,n)/R;,7,A more complicated example,include disciplines.vamsinclude constants.vamsmodule diode(a,c
5、);inout a,c;electrical a,c,int;branch(a,int)res;branch(int,c)dio;parameter real is=10p from(0:inf);parameter real rs=0.0 from 0:inf);parameter real cjo=0.0 from 0:inf);parameter real vj=1.0 from(0:inf);real vd,id,qd;analog begin V(res)+I(res)*rs;vd=V(dio);id=is*(limexp(vd/$vt)-1.0);if(vd vj)begin qd
6、=cjo*vj*(1.0-2.0*sqrt(1.0-vd/vj);end else begin qd=cjo*vd*(1.0+vd/(4.0*vj);end I(dio)+id;I(dio)+ddt(qd);endendmodule,8,=,+,=,=:assigns a VARIABLE vd=V(dio);+:adds a contribution a voltage or current I(dio)+ddt(qd);=:allows to define a DIFFERENTIAL equation for a voltage or current V(n):ddt(V(n)+V(n)
7、=V(lala);,9,How this works,Every ITERATTION of the simulator,it goes thru the analog blocks:this defines the equations the simulator has to solveHighly nonlinear systemThe simulator will usually use iterative methods(eg Newton/Raphson)NEED DERIVATIVES OF STUFF WITH REGARDS TO VOLTAGES AND CURRENTSIt
8、 will AUTOMATICALLY compute them based on the equations that you give,10,YOUR EQUATIONS SHOULD BE DERIBAVLE WITH CONTINUOUS DERIVATIVES,I,V,I,V,SEVERE CONVERGENCE ISSUES,CONVERGENCE ISSUES,I,V,GOOD,11,IF CAN BE DANGEROUS,if(vd=0)begin q=0;end else begin q=vdendFINE IN ALL LANGUAGES BUT NOT IN VERILO
9、GAWILL ASSUME dq/dvd=0 FOR vd=0!,12,Other hazards with automatic derivatives,SQRT has no derivative at 0if(vd vj)begin qd=cjo*vj*(1.0-2.0*sqrt(1.0-vd/vj);end else begin qd=cjo*vd*(1.0+vd/(4.0*vj);EndIN ALL LANGUAGES=WOULD HAVE BEEN FINE BUT NOT IN VERILOGA!,13,Other hazards,abs has non continuous derivativelog is decimal log,ln is natural logSuggestion:always add a comment to remind this when you use log or ln1/2 is 0,like in C(1.0/2.0 is 0.5)Limexp instead of exp if you have convergence issues,
