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1、M/B Design Basics,DWHD-PCA-EE:Tune2008.01.08,Roadmap,M/B Block DiagramsM/B basic components R/L/CM/B basic components ChipsetM/B basic components Super I/OM/B basic components CPUPCIE Introduction8B/10B Coding,M/B Block Diagrams,FSB,DMI,DDR2 channel A,VGA/DVI/HDMI,PCIE X16,USB2.0(12 Ports),SATAII in
2、terface,DDR2 channel B,PCI interface,Com Port,Printer Port,PS/2 Port,Floppy Port,HD Audio,Network PHY I/F,PCIE X1 interface,M/B Block Diagrams Actual M/B,M/B basic components R,Resistor specification,Power Rating:(rated power 70 degree)RC0402 1/16 W RC0603 1/10 W RC0805 1/8 W RC1206 1/4 W,Rated Volt
3、age:the DC or AC(rms)continuous working voltage corresponding tothe rated power is determined by the following formula.,Electrical characteristicoperating temp rangemaximum working voltageMaximum overload voltageDielectric withstanding voltageResistance rangeTemp coefficient,Resistor application on
4、mother board,Jumper for reserved design or debug,often 0 resistor;Pull up or pull down to some logic levelImpedance match for clock and high speed signalFor power,used as damping resistor,power bleed off,M/B basic components CSMD,Capacitor specification,Size:RC0402 RC0603 RC0805 RC1206,Rated Voltage
5、:10V,16V,25V,50V,Electrical features:operating temp range Capacitance tolerance operating temperature Load life case size,capacitor application on mother board,Power decoupling to stabilize a signal or power railEMI signal sink,100pF,150pFRC delay,such as 100nF,1uFHigh speed signal coupling,such as
6、100nF,Tolerance:NPO X5R X7R Y5V M5U,M/B basic components CPTH,Capacitor specification,Parameter:Capacitance ESR,Dissipation Factor Impedance Leakage current,Electrical characteristicoperating temp rangemaximum working voltageMaximum overload voltageDielectric withstanding voltageResistance rangeTemp
7、 coefficient,E-Capacitor application on mother board,Power decoupling,to stabilize power railAudio Signal couplingLow ESR cap,for ripple current filter,Tolerance:Al ECAP OS-CON FP CAP,M/B basic components LSMD,Capacitor specification,Type:Chip inductor Signal Thin Film Chip Inductor Multilayer Chip
8、Inductor Wire Wound Chip Inductor Ferrite bead-EMI Differential mode Common mode Power Inductor,Electrical characteristicoperating temp rangemaximum working voltageMaximum overload voltageDielectric withstanding voltageResistance rangeTemp coefficient,Chip inductor application on mother board,Depres
9、s the noise into power Signal process,impedance matchas a signal filter such as power and VGA signalas EMI filter.USB signal,common mode noise depressFor power process,Tolerance:5%,10%20%,25%,M/B basic components LDIP,Choke specification,Process:IRON Coil PMC,Parameter:L:inductance value RDC:interna
10、l DC resistor IDC:rating current Q:Test Frequency working temperature resonant frequency,Electrical characteristicoperating temp rangemaximum working voltageMaximum overload voltageDielectric withstanding voltageResistance rangeTemp coefficient,choke application on mother board,Power process,DC-DC p
11、ower output chokeEMI filter,DC-DC power input choke,M/B basic components chipset GMCH,Host Interface:FSB GTL Clock,Graphics I/F VGA DVI/HDMI PCIE X16,DMI Interface DMI LINK,Memory Interface DDRII DDR III Maximum 8GB Dual Channel,4-DIMM,NB function on mother board,Host interface to CPU,and make a bri
12、dge between the ICH,Memory,Graphics and CPU.Integrated core:PCI/PCIE bridge,Memory controller,AGP,PCIE/PCI to Host bridgeNB capability:Graphics process:to support the Direct X9.0,10.0 rendering technology Display/Media Content:HDMI/DVI/Display Port,HD-DVD,Blue-Ray Memory speed:to match with memory t
13、ype or speed FSB speed:to match with CPU FSB,M/B basic components chipset ICH,Host Interface:DMI to GMCH pointto-point link,Storage SATAII 3Gb/s RAID,Network Interface LCI/GLCI Ethernet PHY,USB2.0 Interface 12 Ports 6 UHCI 2 EHCI USB legacy support,Expand SlotPCI Rev2.3,3 SlotsPCIE X1,6 Slots,SB fun
14、ction on mother board,Host interface to NB,and make a bridge between the SIO,PCI,PCIE,and NB.Integrated core:PCI/PCIE bridge,PIDE/SATA controller,Audio Link,Network PHY,legacy core:RTC,interrupt controller,SM bus controller,APIC controllerNB capability:Storage:to support the Direct X9.0,10.0 renderi
15、ng technology Expandability:support PCI,PCIE numbers Network:Ethernet PHY Audio Link:AC97,HDA,Audio Interface HAD Link,M/B basic components Super I/O,LPC Interface:connect to SB multi-drop,similar to PCI,Storage Floppy,COM Port Modem serial port Keyboard serial communication,Printer PortLegacy print
16、er port,PS/2 Keyboard Mouse,SIO function on mother board,To provide the communication path for legacy device to ICHIntegrated legacy core:UART,Floppy controller,Printer controller,PS/2 controller,M/B basic components CPU,Desktop Processor,Performance/Features:cores numbers on-chip Shared Cache Size
17、Simultaneous Multi-Threading capability(SMT)FSB/QPI New instructions,Power:65W,95W,130W FMB,Socket:mPGA478 LGA775 socket LGA1336 socket,Process Technology:130 nm,Prescott 90 nm,65 nm,Conroe 45 nm,wolf dale,M/B basic components CPU example,Desktop Bloomfield Processor,Performance/Features:4 cores 8M
18、on-chip Shared Cache Simultaneous Multi-Threading capability(SMT)Intel Quick Path Interconnect(QPI)Integrated Memory Controller(IMC)New instructions,Power:130W FMB,Schedule Q108 First samples Q408 Launch,HEDT Socket:New LGA1336 Socket,Processor Technology:45nm CPU,M/B basic components CPU Trend,Desk
19、top Processor new technology,Fast Radix-16 DividerFaster OS Primitive SupportEnhanced Intel Virtualization Technology,Larger Caches:up to 12 MB24 Way Set Associatively,Intel Wide Dynamic Execution,Intel Advanced Smart Cache,Split Load Cache EnhancementImproved Store ForwardingHigher bus speeds,Intel
20、 SSE4 instructionsSuper Shuffle Engine,Deep Power Down TechnologyEnhanced Intel Dynamic Acceleration Tech,Intel Smart Memory Access,Intel Advanced Digital Media Boost,Intel Intelligent Power Capability,Intel Core Micro architecture,New with the Penryn Family,PCIE Introduction-Key Attributes,Scalable
21、 Width,Frequency Higher Bandwidth,Consolidate the I/O Unify proliferated segments Works in existing PCI Environment,HighPerformance,I/OSimplification,Layered Architecture=longevity Reliability,Availability,Serviceability Advanced Power Management,Virtual Channels Quality of Service/Isochrones,New Fo
22、rm Factors/Innovative Designs Hot Plug/Hot Swap,AdvancedArchitecture,Next Gen 3D/Multimedia,Ease of Use,PCIE Introduction-Architecture,Re-use:IP Houses,Foundries,Tool Vendors,RTL,Compute Industry work:Verification,Interoperability,Design Collateral,Massive Economies of Scale&Investments,PCI Express
23、Targets Chip-to-Chip,Advanced SwitchingTargets Fabrics,PCI PnP Modelinit,enum,config,AS Fabric Mngmtinit,enum,config,PCI SoftwareDriver Model,PEI,PEI,PEI,Physical Layer,Link Layer,Transaction Layer,Layer 4+,MarketSegmentOptimizations,L1/L2Commonality,PCIE Introduction-Transaction Layer,Initializatio
24、n and configuration Packet generation and process service Flow control service Ordering rules Split Transaction Posted and non-posted requests non-posted request require completions Transaction Types Memory,I/O,Configuration,Message,Header,Date,PCIE Introduction-Data Link Layer,Link Management initi
25、alization and power management Data integrity Data protection,error checking,and retry services TLP sequence number Data Protection Code,Header,Date,Seq.#,CRC,PCIE Introduction-Physical Layer,Initialization and configuration Packet generation and process service Flow control service Ordering rules,H
26、eader,Date,Seq.#,CRC,Framing,Framing,PCIE Introduction-Definitions,8B/10B Coding-Part 1 History/application,The code was described in 1983 by Al Widmer and Peter Franaszek in the IBM Journal of Research and Development.IBM was issued a patent for the scheme the following year.IBMs patent notwithstan
27、ding,the method,implementation and goals are very similar to Group Code Recording(GCR)used on floppy disks in some computers during late 1970s/early 80s,History,Application,PCI Express IEEE 1394b Serial ATA SAS Fiber Channel SSA Hyper Transport,InfiniBand XAUI Serial RapidIO DVI(Transition Minimized
28、 Differential Signaling)DVB Asynchronous Serial Interface(ASI)Gigabit Ethernet(except for the twisted pair based 1000Base-T),8B/10B Coding-Part 2 How it works,How it works,As the scheme name suggests,8 bits of data are transmitted as a 10-bit entity called a symbol,or character.The low 5 bits of dat
29、a are encoded into a 6-bit group and the top 3 bits are encoded into a 4-bit group.These code groups are concatenated together to form the 10-bit symbol that is transmitted on the wire.Because 8b/10b encoding uses 10-bit symbols to encode 8-bit words,some of the possible 1024 codes can be excluded t
30、o grant a run-length limit of 5 consecutive equal bits and grant that the difference of the count of 0s and 1s is no more than 2.Some of the 256 possible 8-bit words can be encoded in two different ways.Using these alternative encodings,the scheme is able to affect long-term DC-balance in the serial
31、 data stream.The encoding is normally done entirely in hardware.Upper layers of the software stack should be unaware that this encoding is being used.,8B/10B Coding-Part 2 Code Table,3B/4B,Note 1:For D.x.7,the Primary(D.x.P7)or Alternate(D.x.A7)encoding must be selected in order to avoid a run of fi
32、ve consecutive 0s or 1s when combined with the preceding 5b/6b code.Sequences of five identical bits are used in comma codes for synchronization issues.D.x.A7 is only used for x=17,x=18 and x=20 when RD=-1 and for x=11,x=13 and x=14 when RD=+1.With x=23,x=27,x=29 and x=30,the same code forms the con
33、trol codes K.x.7.Any other x.A7 code cant be used as it would result in chances for misaligned comma sequences.Note 2:The alternate encoding for the K.x.y codes with disparity 0 allow for K.28.1,K.28.5 and K.28.7 to be comma codes that contain a bit sequence that cant be found elsewhere in the data stream,8B/10B Coding-Part 2 Code Table,5B/6B,8B/10B Coding-Part 2 Code Table,Control symbols,
