《IC Mask Design Training.ppt》由会员分享，可在线阅读，更多相关《IC Mask Design Training.ppt（74页珍藏版）》请在三一办公上搜索。
1、Welcome to IC Mask Design Training,2,Fabrication Process,3,Agenda,What we want!Steps involved in the fabrication processN-Well ProcessP-Well ProcessTwin Tub Process,4,What we want!,5,Lets fabricate this first!,6,Steps involved in the fabrication process,Crystal GrowthEpitaxial GrowthFilm FormationLi
2、thographyEtchingImpurity Doping,7,Crystal Growth,Techniques for growing single crystals of Silicon to form a Wafer.,8,General Procedure,9,Single Crystal Silicon growth,Czochralski methodSilicon crystal growth from the Melt 90%of the the semiconductor industry use this option.Starting Material:Quartz
3、ite Pure form of Sand(SiO2),10,Czochralski Method(Contd),SiO2 is heated in a furnace along with various forms of carbon like coal,coke and wood chips SiC+SiO2 Si+SiO+COThis produces a metallurgical-grade Silicon with a purity of about 98%,11,Czochralski Method(Contd),Solid Silicon is pulverized and
4、treated with Hydrogen Chloride(HCl)Si+3HCl SiHCl3+H2TriChloroSaline(SiHCl3)is liquid at room temperatureFractional distillation removes unwanted impurities,12,Czochralski Method(Contd),Electronic grade Silicon(EGS)is got by hydrogen reduction of SiHCl3 SiHCl3+H2 Si+3HClThis reaction takes place in a
5、 reactor with resistance-heated Silicon rod on which the deposition takes place.,13,Czochralski Method(Contd),ECG is a polycrystalline material of high purity(impurity concentration is in the order of parts-per-billion)is the raw material for device-quality single crystal Silicon,14,Czochralski Meth
6、od(Contd),Crystal PullerThree main parts A furnace which includes a fused-silicon(SiO2)crucible,a graphite susceptor,a rotation mechanism,a heating element and a power supply,15,Czochralski Method(Contd),A crystal pulling mechanism contains a seed holder and a counter-clockwise rotating mechanismAn
7、Ambient control a gas source(argon),a flow control and a exhaust system,16,Czochralski Method(Contd),Crystal growing process-Polycrystalline Silicon(EGS)is placed in the crucible and heated to its melting point-A suitably oriented seed-crystal is is suspended in the crucible,17,Czochralski Method(Co
8、ntd),-the seed crystal is slowly withdrawn-Progressive freezing at the solid-liquid interface yields a large,single crystal called Ingot-typical pull rate is a few millimeters per minute-a know amount of dopant is added to the melt to obtain the desired doping concentration-For Silicon born and phos
9、phorus are the common dopants for p and n type materials,18,Material Characterization,Wafer ShapingCrystal characterization,19,Material Characterization(Contd),Wafer Shaping-the two ends are removed-the surface is grinded to to give the required diameter-one or more flat regions grounded along the l
10、ength of the ingot-ingots are diamond sawed to give wafers,20,Material Characterization(Contd),-Slicing determines four wafer parameter Surface orientation Thickness(0.5-0.7 mm)Taper Bow-both the sides are lapped with a mixture of Al2O3 and glycerin,21,Material Characterization(Contd),-the damaged a
11、nd contaminated regions are removed using chemical etching-polished to provide a smooth and specular surface,22,Material Characterization(Contd),Crystal characterization-Crystal defects-Material properties,23,Material Characterization(Contd),Crystal Defects-Point defects-Line defects-Area defects,24
12、,Material Characterization(Contd),Material Properties-Resistivity-Minority carrier lifetime-Trace impurities such as oxygen and carbon-Surface flatness-Slice Taper-Slice Bow,25,Epitaxial Growth,Growth of crystal of one mineral on another to achieve same structural orientationMethods-Chemical-Vapor D
13、eposition,26,Chemical-Vapor Deposition,Also know as Vapor-Phase epitaxySilicon Tetrachloride(SiCl4),Dichlorosilane(SiH2Cl2),trichlorosilane(SiHCl3)and Silane(SiH4)are used SiCl4+2H2 Si+4HCl,27,Chemical-Vapor Deposition,A competing reaction also takes place SiCl4+Si 2SiCl2Etching will take place if t
14、he concentration is too high.,28,Chemical-Vapor Deposition(Contd),Diborane(B2H6)is used as p-type dopant Phospine(PH3)or Arsine(AsH3)is used for n-type,29,Film Formation,Several different layers of thin film need to be fabricated during IC fabricationThin films can be classified as-Thermal Oxides-Di
15、electric layers-Polycrystalline Silicon-Metal FilmsChemical-Mechanical Polishing,30,Film Formation(Contd),31,Thermal Oxidation,Gate-oxide and Field-oxide fall are grown using this techniqueGate-Oxide is the layer below which a conducting channel is formed between source and drainField-Oxide provides
16、 isolation from other devicesGate-Oxide and Field-Oxide are grown using thermal oxidation,32,Thermal Oxidation(Contd),Setup of Thermal Oxidation-Filtered flow of air is maintained is maintained at one end of the cylindrical tube.This minimizes dust and particulate matters in the air surrounding the
17、wafers and minimize contamination during wafer loading-Oxidation temperature is generally 9000c 12000c,33,Thermal Oxidation(Contd),-Oxidation system uses microcomputers to regulate the gas flow sequence,automatic insertion and removal of wafers,to ramp temperature,to maintain the oxidation temperatu
18、re-Dry Oxidation Si+O2 SiO2-Wet Oxidation Si+2H2O SiO2+2H2,34,Dielectric Deposition,Used for deposition of insulation layer and the passivation layerThree commonly used methods-Atmosphere-pressure CVD-Low-Pressure CVD-Plasma-enhanced CVD,35,Dielectric Deposition(Contd),Setup of Atmospheric-Pressure
19、CVD and Low-Pressure CVD are similar to the Thermal oxidation chamber.The gases used are different.Setup of Plasma-Enhanced CVD-RF voltage causes the plasma discharge-Temperature is maintained at 100-4000c using resistance heater,36,Silicon Dioxide Deposition,Used to insulate multilevel metallizatio
20、n,to mask ion implantation diffusion and to increase the thickness of the thermally grown SiO2 For low temperature(300-5000C)deposition,film is formed by reacting Silane(SiH4)and oxygen SiH4+O2 SiO2+2H2,37,Silicon Dioxide Deposition(Contd),For intermediate temperature(500-8000C)deposition,TetraEthyl
21、OrthoSilicate(Si(OC2H5)4)is decomposed in a LPCVD Si(OC2H5)4 SiO2+by-productsFor high temperature(9000C)deposition,SiO2 is deposited by reacting DiChloroSilane(SiCl2H2)with Nitrous oxide(N2O)SiCl2H2+2N2O SiO2+2N2+2HCl,38,Silicon Nitride Deposition,Acts as good barrier for water and sodium,excellent
22、scratch protection,as mask for selective oxidation of siliconIn LCPVD process,DiChloroSilane and ammonia react at 700-8000C to deposit Silicon Nitride3SiCl2H2+4NH3 Si3N4+6HCl+6H2,39,Silicon Nitride Deposition(Contd),Silicon Nitride is formed by reacting Silane and ammonia in an argon discharge or Ni
23、trogen discharge Plasma-Enhanced CVDSiH4+NH3 SiNH+3H22SiH4+N2 2SiNH+3H2,40,PolySilicon Deposition,Used as gate electrode,high value resistor and also as conductor for shot lengthLPCVD operating at 600-6500C is used to react pyrolyzing silane according to the following reactionSiH4 Si+2H2,41,Metalliz
24、ation,Physical vapor deposition-Evaporation and E-Beam EvaporationWhen a source of material is heated above its melting evaporation occurs.The evaporated atoms travel at high velocity and gets settled on the wafer surface.The heating is done through resistance heating,rf heating or through the use o
25、f electron beam,42,Metallization(Contd),-Ion Beam SputteringA source of Ion beam is accelerated and impinged on the surface of the semiconductor wafer.Magnetic field is used to increase the efficiencyChemical vapor deposition(CVD)is also used for certain metals,43,Chemical-Mechanical Polishing,Used
26、for global planarizationIt consists of the sample surface against a pad that carries slurry between themAbrasive materials in the slurry cause mechanical damage on the sample surface loosening the material for enhanced chemical attack or fracturing of the pieces of the surface into slurry where they
27、 dissolved or swept away,44,Lithography,Lithography is the process of transferring patterns of geometric shapes on a mask to a thin layer of radiation-sensitive material called photo-resist covering the surface of a semiconductor wafer.These patterns define the various regions of a integrated circui
28、tAnd you as a IC Layout mask designer will be defining these mask,45,Optical Lithography,Vast majority of lithographic equipments for IC fabrication is Optical equipments using ultraviolet light,46,The Clean Room,Clean rooms are necessary because dust particles in the air can settle on semiconductor
29、 wafers and the lithographic masks and can cause defects in the devices,which will result in the circuit failureThe total number of dust particles,the temperature and the humidity are controlled in a clean room,47,The Clean Room(Contd),Two systems to define a clean room1.English system the numerical
30、 designation of the class is taken from the maximum allowable number of particles 0.5m and larger,per cubic foot2.Metric system the class is taken form the logarithm(base 10)of the maximum allowable number of particles 0.5m and larger,per cubic meter,48,Exposure Tools,The pattern transfer process is
31、 accomplished by using a lithographic exposure toolThree parameters define the performance-Resolution-Registration-Throughput,49,Exposure Tools(Contd),Resolution is the minimum feature dimension that can be transferred with high fidelity to a resist film on a semiconductor waferRegistration is a mea
32、sure of how accurately patterns on successive masks can be aligned(or overlaid)with respect to the previously defined patterns on waferThroughput is the number of wafers that can be exposed per hour for a given mask level,50,Exposure Tools(Contd),Two optical methods-Shadow printing-Projection printi
33、ng,51,Exposure Tools(Contd),Shadow printing-Contact printing The mask and the wafer are in direct contact-Proximity printing-The mask and the wafer are in close proximity,52,Exposure Tools(Contd),Projection printing-The mask patterns are projected on to the resisted-coated wafer many centimeters awa
34、y form the mask-To increase resolution only a small portion of the mask is exposed at a time and the area is scanned or stepped over the wafer to cover the entire surface,53,Exposure Tools(Contd),Four methods-Annual-field wafer scan-1:1 Step-and-Repeat-M:1 reduction step-and-repeat-M:1 reduction ste
35、p-and-scan,54,Exposure Tools(Contd),Ultraviolet source-High-pressure mercury-arc lamp is widely used 436nm 0.3m-KrF excimer laser 248nm 0.18m-ArF excimer laser 193nm 0.10m-F2 excimer laser 157nm 0.07m,55,Masks,Using EDA tools,layout designers completely describe the circuit patterns electricallyThe
36、digital data produced by the EDA tool then drives a pattern generator,which is an electron-beam lithographic system that transfers the patterns directly to electron-sensitized mask,56,Masks(Contd),The mask consists of a fused silica substrate covered with chromium layer.15x15cm2 in size and 0.6cm in
37、 thicknessThe pattern on a mask defines one level of an IC design.The composite layout is broken into mask levels that correspond to the IC process sequenceTypically 15-20 different mask levels are required for a complete IC process cycle,57,Masks(Contd),Defects can be introduced during the manufact
38、ure of mask or during the subsequent lithographic processesYield is defined as the ratio of number of good chips to the total number of chips per wafer y=e DA,where D(Defect Density)is the average number of fatal defects per unit area and A is the area of a chipFor a N level mask the final yield is
39、y=e-NDA,58,Photoresist,A radiation-sensitive compoundTypes-Positive resists The exposed region becomes more soluble and can be removed of more easily during development.The pattern formed is same as on the mask-Negative resists The exposed regions become less soluble and the pattern formed is the re
40、verse of that on the mask,59,Photoresist(Contd),Positive resist-Consists of a photosensitive compound,a base resin and an organic solvent-Prior to exposure the photosensitive compound is insoluble in the developer solution.After exposure,the photosensitive compound absorbs the radiations,changes its
41、 chemical structure and becomes soluble in the developer solution,60,Photoresist(Contd),Negative resist-Consists of polymers combined with a photosensitive compound-After exposure,the photosensitive compound absorbs the optical energy and converts it into chemical energy to initiate a polymer linkin
42、g reaction.These cross-linked polymers become insoluble in the developer,61,Etching,Cleaning of the wafer to remove contamination that results from handling and storing and also for selective removal of certain portion of the deposited material on a waferThe material to be removed can be the contami
43、nation,insulating layer,the photoresist,the metal layers et alTwo methods are:-Wet Chemical etching-Dry or Plasma Etching,62,Wet Chemical Etching,Three basic steps are involved-The reactants are transported by diffusion to the reacting surface-Chemical reaction occurs at the surface-The products for
44、m the surface are removed by diffusion,63,Wet Chemical Etching(Contd),Silicon Etching-First the silicon is oxidized using Nitric acid in water or acetic acid(CH3COOH)Si+4NHO3 SiO2+2H2O+4NO2-HydroFluoric acid is used to dissolve the SiO2 layerSiO2+6HF H2 SiF6+2H2OPolysilicon etching is similar to Si
45、etching except the rate of etching is faster and hence need to be controlled precisely,64,Wet Chemical Etching(Contd),Silicon Dioxide Etching-SiO2 etching is accomplished using a dilute solution of HydroFluoric acid SiO2+6HF H2+SiF6+2H2OSilicon Nitride Etching-Si3N4 is etched using HydroFluoric(HF)a
46、cid and Phosphoric acid(H3PO4),65,Wet Chemical Etching(Contd),Aluminum Etching-Etched using heated solutions of Phosphoric acid,Nitric acid,acetic acid and DI water-Nitric acid(HNO3)oxidizes the aluminum and then the oxide is dissolved in Phosphoric acid(H3PO4),66,Dry or Plasma Etching,Plasma is a f
47、ully or partially ionized gas compoundWhen an electric field of sufficient magnitude is applied to a gas,the gas breakdowns and becomes ionized,67,Plasma Etching(Contd),Plasma Etching process takes place in 5 steps-The etchant species is generated in plasma-The reactant is then transported by diffus
48、ion through the stagnant gas layer to the surface-The reactant is absorbed on the surface-Chemical reaction takes place to form a volatile compound-The compounds are desorbed in from the surface,diffused into the bulk gas and pumped out of the system,68,Plasma Etching(Contd),Two methods-Physical Met
49、hodPositive Ions bombard the surface at high velocity-Chemical MethodNeutral reactive species generated by the plasma interact with the material surface to form volatile products,69,Impurity Doping,Introduction of controlled amounts of impurity dopants into the semiconductor.This changes the electri
50、cal properties of the semiconductorsTwo methods-Diffusion-Ion Implantation,70,Diffusion,Dopant atoms are placed on or near the surface of the wafer by deposition from the gas phase of the dopant or by using doped-oxide sourcesAt elevated temperatures,the dopant diffuses into the wafer because of hig
