Verilog课程设计洗衣机设计电路.docx

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1、Verilog课程设计洗衣机设计电路 Verilog课程设计-洗衣机控制器 设计要求：设计一个电子定时器，控制洗衣机作如下运转：定时启动-正转20秒-暂停10秒-反转20秒-暂停10秒-定时未到，回到“正转20秒-暂停10秒-反转20秒-暂停10秒”；若定时到,则停机发出音响信号。用两个数码管显示洗涤的预置时间，按倒计时的方式计时，直到时间到停机；洗涤过程由“开始”信号开始。三只LED灯表示“正转”、“反转”、“暂停”三个状态。 设计过程中用三个表示状态的寄存器zz、fz、pause，以及三个寄存器表示LED灯,LED1表示zz；LED2表示fz；LED3表示pause。 用data_out1

2、,data_out2显示预置时间。Beep为音响信号。 实验源程序如下： timescale 1ns/1ns /源程序的测试文件 module tb_wash; parameter DELY=5; reg clk,start,sure; reg6:0count0; wire beep,led1,led2,led3,zz,fz,pause; wire 6:0data_out1,data_out2; wash C1(data_out1,data_out2,beep,led1,led2,led3,zz,fz,pause,start,count0,sure,clk); initial begin st

3、art=0; sure=0; count0=7b0000111; #DELY start=1; #(DELY*10) sure=1; #(DELY*20) sure=0; end always begin clk=0; #(DELY*2) clk=clk; #(DELY*2) clk=clk;/产生振荡时钟 end initial #(DELY*3000)$finish; endmodule module wash(data_out1,data_out2,beep,led1,led2,led3,zz,fz,pause,start,count0,sure,clk); input clk,sure

4、;/sure用于输入数据之后的确定键，确定后洗衣机开始工作 input6:0count0;/count0输入洗涤时间 input start;/电源开关 output 6:0data_out1,data_out2;/数码管时间输出 reg 6:0data_out1,data_out2; output zz,fz,pause; reg zz,fz,pause; output led1,led2,led3; reg led1,led2,led3; reg5:0counts; output beep; /音响 reg beep; reg6:0count;/计数分钟 reg3:0countm;/计数秒

5、 wire 3:0bcd_1; reg 3:0bcd_2; reg signal;/用于控制音响信号 initial begin data_out1=7b0; data_out2=7b0; counts=6b0; countm=4b0; count=count0; bcd_2=4b0; zz=0;fz=0;pause=0; beep=0; led1=0;led2=0;led3=0; signal=0; end always(posedge clk) begin if(sure=1) begin signal=1; count0)&(start=1)&(signal=1) begin if(co

6、unts=6b111100)/60 begin counts=6b1; count=count-1; end else begin counts=counts+1b1; if(counts=5b10100) /20 begin zz=1;fz=0;pause=0; led1=1;led2=0;led3=0; end else if(counts6b110010&counts=6b111011)/30 5059 begin pause=1;zz=0;fz=0; led2=1;led1=0; led3=0; end else begin fz=1;zz=0;pause=0; led3=1;led1

7、=0; led2=0; end end end if(signal=1&count=0)/控制洗涤结束时音响响的时间 begin if(countm=4b1001) beep=0; else begin countm=countm+1; beep=7d90) bcd_2=7d80) bcd_2=7d70) bcd_2=7d60) bcd_2=7d50) bcd_2=7d40) bcd_2=7d30) bcd_2=7d20) bcd_2=7d10) bcd_2=4d1; else bcd_2=4d0; end assign bcd_1=count-bcd_2*4d10; always(bcd_1

8、)/数码管个位的显示 begin case (bcd_1) 4b0000:data_out1=7b0111111;/0 4b0001:data_out1=7b0000110; 4b0010:data_out1=7b1011011; 4b0011:data_out1=7b1001111; 4b0100:data_out1=7b1100110; 4b0101:data_out1=7b1101101; 4b0110:data_out1=7b1111100; 4b0111:data_out1=7b0000111; 4b1000:data_out1=7b1111111; 4b1001:data_out1

9、=7b1100111; default:data_out1=7b0000000; endcase end always(bcd_2)/数码管十位的显示 begin case (bcd_2) 4b0000:data_out2=7b0111111;/0 4b0001:data_out2=7b0000110; 4b0010:data_out2=7b1011011; 4b0011:data_out2=7b1001111; 4b0100:data_out2=7b1100110; 4b0101:data_out2=7b1101101; 4b0110:data_out2=7b1111100; 4b0111:

10、data_out2=7b0000111; 4b1000:data_out2=7b1111111; 4b1001:data_out2=7b1100111; default:data_out2=8b0000000; endcase end endmodule 程序编号之后在linux系统的nclaunch里面仿真出来波形如下： 波形符合设计的要求。 仿真结束后到linux系统里面DC里面综合，综合的电路图如下: 综合后会有检查综合结果报表AREA。面积报表中包含了综合之后的各个模块的面积，报表如下： 综合之后保存wash_post.v文件。利用测试文件对其进行后仿真，仿真的波形如下图 由于是后仿真

11、，综合的时候考虑的各个门级之间时间延迟，所以后综合的时间延迟包含了从输入到输出的总的时间延迟。产生的时间报表如下 综合之后保存文件为.v文件，文件将保存综合出来之后的具体门级电路形式，综合之后产生的门级网表： module SNPS_CLOCK_GATE_HIGH_wash_0 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net58, net60, net61, net64; assign net58 = CLK; assign ENCLK = net60; assign net61 = EN; AND2HD4X main_gat

12、e ( .A(net64), .B(net58), .Z(net60) ); LATNHDLX latch ( .D(net61), .GN(net58), .Q(net64) ); endmodule module SNPS_CLOCK_GATE_HIGH_wash_3 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net58, net60, net61, net64; assign net58 = CLK; assign ENCLK = net60; assign net61 = EN; AND2HD4X main_gate (

13、 .A(net64), .B(net58), .Z(net60) ); LATNHDLX latch ( .D(net61), .GN(net58), .Q(net64) ); endmodule module SNPS_CLOCK_GATE_HIGH_wash_2 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net58, net60, net61, net64; assign net58 = CLK; assign ENCLK = net60; assign net61 = EN; AND2HD4X main_gate ( .A

14、(net64), .B(net58), .Z(net60) ); LATNHDLX latch ( .D(net61), .GN(net58), .Q(net64) ); endmodule module SNPS_CLOCK_GATE_HIGH_wash_1 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net58, net60, net61, net64; assign net58 = CLK; assign ENCLK = net60; assign net61 = EN; AND2HD4X main_gate ( .A(ne

15、t64), .B(net58), .Z(net60) ); LATNHDLX latch ( .D(net61), .GN(net58), .Q(net64) ); endmodule module wash ( data_out1, data_out2, beep, led1, led2, led3, zz, fz, pause, start, count0, sure, clk ); output 6:0 data_out1; output 6:0 data_out2; input 6:0 count0; input start, sure, clk; output beep, led1,

16、 led2, led3, zz, fz, pause; wire N7, N10, N11, N12, N13, N14, N15, N16, N18, N25, N26, N27, N28, N29, N30, N31, N40, N41, N42, N43, N44, N45, N46, N47, N48, N49, N53, N54, N55, N58, N59, N60, N95, N96, N97, N158, N175, N177, N178, N179, N180, N181, N182, net70, net75, net80, net85, add_48_aco/carry5

17、 , add_48_aco/carry4 , add_48_aco/carry3 , add_48_aco/carry2 , mult_add_48_aco/PROD_not0 , mult_add_48_aco/PROD_not1 , mult_add_48_aco/PROD_not2 , mult_add_48_aco/PROD_not3 , mult_add_48_aco/PROD_not4 , mult_add_48_aco/PROD_not5 , n92, n93, n94, n95, n96, n97, n98, n99, n100, n101, n102, n103, n104,

18、 n105, n106, n107, n108, n109, n110, n111, n112, n113, n114, n115, n116, n117, n118, n119, n120, n121, n122, n123, n124, n125, n126, n127, n128, n129, n130, n131, n132, n133, n134, n135, n136, n137, n138, n139, n140, n141, n142, n143, n144, n145, n146, n147, n148, n149, n150, n151, n152, n153, n154,

19、 n155, n156, n157, n158, n159, n160, n161, n162, n163, n164, n165, n166, n167, n168, n169, n170, n171, n172, n173, n174, n175; wire 6:0 count; wire 5:0 counts; wire 3:0 countm; wire 3:0 bcd_2; FFDQHD2X counts_reg0 ( .D(N26), .CK(net75), .Q(counts0) ); FFDQHD2X counts_reg1 ( .D(N27), .CK(net75), .Q(c

20、ounts1) ); FFDQHD2X counts_reg2 FFDQHD2X counts_reg3 FFDQHD2X counts_reg4 FFDQHD2X counts_reg5 ( .D(N28), .CK(net75), .Q(counts2) ); ( .D(N29), .CK(net75), .Q(counts3) ); ( .D(N30), .CK(net75), .Q(counts4) ); ( .D(N31), .CK(net75), .Q(counts5) ); FFDQHD2X count_reg0 ( .D(N40), .CK(net85), .Q(count0)

21、 ); FFDQHD2X count_reg1 ( .D(N41), .CK(net85), .Q(count1) ); FFDQHD2X count_reg2 ( .D(N42), .CK(net85), .Q(count2) ); FFDQHD2X count_reg3 ( .D(N43), .CK(net85), .Q(count3) ); FFDQHD2X count_reg4 ( .D(N44), .CK(net85), .Q(count4) ); FFDQHD2X count_reg5 ( .D(N45), .CK(net85), .Q(count5) ); FFDQHD2X co

22、unt_reg6 ( .D(N46), .CK(net85), .Q(count6) ); FFJKHD4X countm_reg0 ( .J(1b1), .K(1b1), .CK(net80), .Q(countm0), .QN(n99) ); FFDQHD2X countm_reg1 ( .D(N53), .CK(net80), .Q(countm1) ); FFDQHD2X countm_reg2 ( .D(N54), .CK(net80), .Q(countm2) ); FFDQHD2X countm_reg3 ( .D(N55), .CK(net80), .Q(countm3) );

23、 FFEDQHD4X beep_reg ( .D(N158), .E(N49), .CK(clk), .Q(beep) ); FFDQHD2X fz_reg ( .D(N25), .CK(net70), .Q(fz) ); FFDQHD2X led1_reg ( .D(N18), .CK(net70), .Q(led1) ); FFDQHD2X zz_reg ( .D(N18), .CK(net70), .Q(zz) ); FFDQHD2X led3_reg ( .D(N25), .CK(net70), .Q(led3) ); FFEDQHD4X pause_reg ( .D(N59), .E

24、(N58), .CK(clk), .Q(pause) ); FFEDQHD4X led2_reg ( .D(N59), .E(N58), .CK(clk), .Q(led2) ); SNPS_CLOCK_GATE_HIGH_wash_0 clk_gate_fz_reg ( .CLK(clk), .EN(N48), .ENCLK( net70) ); SNPS_CLOCK_GATE_HIGH_wash_3 clk_gate_counts_reg ( .CLK(clk), .EN(N7), .ENCLK(net75) ); SNPS_CLOCK_GATE_HIGH_wash_2 clk_gate_

25、countm_reg ( .CLK(clk), .EN(N60), .ENCLK(net80) ); SNPS_CLOCK_GATE_HIGH_wash_1 clk_gate_count_reg ( .CLK(clk), .EN(N47), .ENCLK(net85) ); HAHD4X add_48_aco/U1_1_1 ( .A(N178), .B(N177), .CO(add_48_aco/carry2 ), .S(N27) ); HAHD4X add_48_aco/U1_1_2 ( .A(N179), .B(add_48_aco/carry2 ), .CO( add_48_aco/ca

26、rry3 ), .S(N28) ); HAHD4X add_48_aco/U1_1_3 ( .A(N180), .B(add_48_aco/carry3 ), .CO( add_48_aco/carry4 ), .S(N29) ); HAHD4X add_48_aco/U1_1_4 ( .A(N181), .B(add_48_aco/carry4 ), .CO( add_48_aco/carry5 ), .S(N30) ); INVHD1X U107 ( .A(count0), .Z(N10) ); NAND2B1HD1X U108 ( .AN(count1), .B(N10), .Z(n92

27、) ); OAI21B2HD1X U109 ( .AN(count0), .BN(count1), .C(n92), .Z(N11) ); OR2HD1X U110 ( .A(n92), .B(count2), .Z(n93) ); OAI21B2HD1X U111 ( .AN(n92), .BN(count2), .C(n93), .Z(N12) ); NOR2HD1X U112 ( .A(n93), .B(count3), .Z(n96) ); AOI21HD1X U113 ( .A(n93), .B(count3), .C(n96), .Z(n94) ); INVHD1X U114 (

28、.A(n94), .Z(N13) ); INVHD1X U115 ( .A(count4), .Z(n95) ); NAND2HD1X U116 ( .A(n96), .B(n95), .Z(n97) ); OAI21HD1X U117 ( .A(n96), .B(n95), .C(n97), .Z(N14) ); XNOR2HD1X U118 ( .A(count5), .B(n97), .Z(N15) ); NOR2HD1X U119 ( .A(count5), .B(n97), .Z(n98) ); XOR2HD1X U120 ( .A(count6), .B(n98), .Z(N16)

29、 ); NAND2HD1X U121 ( .A(counts0), .B(N175), .Z(mult_add_48_aco/PROD_not0 ) ); INVHD1X U122 ( .A(mult_add_48_aco/PROD_not0 ), .Z(N177) ); NAND2HD1X U123 ( .A(counts1), .B(N175), .Z(mult_add_48_aco/PROD_not1 ) ); INVHD1X U124 ( .A(mult_add_48_aco/PROD_not1 ), .Z(N178) ); NAND2HD1X U125 ( .A(counts2),

30、.B(N175), .Z(mult_add_48_aco/PROD_not2 ) ); INVHD1X U126 ( .A(mult_add_48_aco/PROD_not2 ), .Z(N179) ); NAND2HD1X U127 ( .A(counts3), .B(N175), .Z(mult_add_48_aco/PROD_not3 ) ); INVHD1X U128 ( .A(mult_add_48_aco/PROD_not3 ), .Z(N180) ); NAND2HD1X U129 ( .A(counts4), .B(N175), .Z(mult_add_48_aco/PROD_

31、not4 ) ); INVHD1X U130 ( .A(mult_add_48_aco/PROD_not4 ), .Z(N181) ); NAND2HD1X U131 ( .A(N175), .B(counts5), .Z(mult_add_48_aco/PROD_not5 ) ); INVHD1X U132 ( .A(mult_add_48_aco/PROD_not5 ), .Z(N182) ); INVHD1X U133 ( .A(N177), .Z(N26) ); XOR2HD1X U134 ( .A(add_48_aco/carry5 ), .B(N182), .Z(N31) ); X

32、OR2HD4X U135 ( .A(N95), .B(bcd_22), .Z(N97) ); NAND2HD1X U136 ( .A(n100), .B(n101), .Z(data_out26) ); OAI21HD1X U137 ( .A(N96), .B(N95), .C(n100), .Z(data_out25) ); AOI21HD1X U138 ( .A(bcd_22), .B(n102), .C(bcd_23), .Z(n100) ); NAND3B1HD1X U139 ( .AN(data_out24), .B(n101), .C(n103), .Z(data_out23) )

33、; NAND3HD1X U140 ( .A(bcd_22), .B(n104), .C(N95), .Z(n103) ); OAI22HD1X U141 ( .A(N95), .B(n104), .C(N95), .D(n105), .Z(data_out24) ); NAND3B1HD1X U142 ( .AN(N95), .B(n105), .C(n106), .Z(data_out22) ); NAND2HD1X U143 ( .A(n104), .B(n106), .Z(n105) ); INVHD1X U144 ( .A(N96), .Z(n104) ); OAI211HD1X U1

34、45 ( .A(N96), .B(N95), .C(n102), .D(bcd_22), .Z(data_out21) ); NAND2HD1X U146 ( .A(N96), .B(N95), .Z(n102) ); NAND3HD1X U147 ( .A(n107), .B(n101), .C(n108), .Z(data_out20) ); XNOR2HD1X U148 ( .A(n106), .B(N95), .Z(n108) ); NAND2HD1X U149 ( .A(N96), .B(n106), .Z(n101) ); NAND2HD1X U150 ( .A(n109), .B

35、(n110), .Z(data_out16) ); OAI21HD1X U151 ( .A(n111), .B(n112), .C(n109), .Z(data_out15) ); INVHD1X U152 ( .A(n113), .Z(n109) ); OAI21HD1X U153 ( .A(n114), .B(n115), .C(n116), .Z(n113) ); INVHD1X U154 ( .A(n117), .Z(data_out14) ); NAND3HD1X U155 ( .A(n110), .B(n117), .C(n118), .Z(data_out13) ); NAND3

36、HD1X U156 ( .A(n119), .B(count0), .C(n120), .Z(n118) ); AOI22HD1X U157 ( .A(n111), .B(n121), .C(n122), .D(n123), .Z(n117) ); OAI211HD1X U158 ( .A(n124), .B(n122), .C(n115), .D(n125), .Z(data_out12) ); INVHD1X U159 ( .A(n119), .Z(n115) ); OAI211HD1X U160 ( .A(n111), .B(n112), .C(n126), .D(n125), .Z(d

37、ata_out11) ); INVHD1X U161 ( .A(n123), .Z(n125) ); OAI21HD1X U162 ( .A(n114), .B(n127), .C(n128), .Z(n126) ); NOR2HD1X U163 ( .A(n122), .B(n120), .Z(n114) ); INVHD1X U164 ( .A(n111), .Z(n120) ); INVHD1X U165 ( .A(count0), .Z(n122) ); INVHD1X U166 ( .A(n121), .Z(n112) ); NAND3HD1X U167 ( .A(n116), .B

38、(n110), .C(n129), .Z(data_out10) ); AOI22HD1X U168 ( .A(n119), .B(count0), .C(n121), .D(n127), .Z(n129) ); NOR2HD1X U169 ( .A(n124), .B(count0), .Z(n121) ); NOR2HD1X U170 ( .A(n127), .B(n124), .Z(n119) ); NAND3HD1X U171 ( .A(n128), .B(n111), .C(n127), .Z(n110) ); INVHD1X U172 ( .A(n130), .Z(n127) );

39、 NAND2HD1X U173 ( .A(n123), .B(n124), .Z(n116) ); INVHD1X U174 ( .A(n128), .Z(n124) ); XNOR2HD1X U175 ( .A(n131), .B(n132), .Z(n128) ); AOI22HD1X U176 ( .A(n133), .B(n134), .C(N96), .D(n135), .Z(n132) ); NAND2B1HD1X U177 ( .AN(N96), .B(n136), .Z(n133) ); XNOR2HD1X U178 ( .A(count3), .B(N97), .Z(n131

40、) ); NOR2HD1X U179 ( .A(n111), .B(n130), .Z(n123) ); XOR2HD1X U180 ( .A(n135), .B(n137), .Z(n130) ); XNOR2HD1X U181 ( .A(n134), .B(N96), .Z(n137) ); INVHD1X U182 ( .A(n136), .Z(n135) ); OAI21HD1X U183 ( .A(N95), .B(n138), .C(n136), .Z(n111) ); NAND2HD1X U184 ( .A(N95), .B(n138), .Z(n136) ); INVHD1X

41、U185 ( .A(n106), .Z(bcd_22) ); AOI22HD1X U186 ( .A(n139), .B(n140), .C(n107), .D(n141), .Z(n106) ); INVHD1X U187 ( .A(bcd_23), .Z(n107) ); OAI22HD1X U188 ( .A(bcd_23), .B(n140), .C(n142), .D(n139), .Z(N96) ); OAI221HDLX U189 ( .A(n143), .B(n139), .C(bcd_23), .D(n144), .E(n145), .Z( N95) ); AOI22HD1X

42、 U190 ( .A(count6), .B(n146), .C(n142), .D(n147), .Z(n145) ); NAND2HD1X U191 ( .A(n148), .B(n149), .Z(n147) ); AOI211HD1X U192 ( .A(count4), .B(count2), .C(n150), .D(n151), .Z(n142) ); INVHD1X U193 ( .A(n143), .Z(n151) ); NAND2HD1X U194 ( .A(n152), .B(n148), .Z(n146) ); NAND2HD1X U195 ( .A(count3), .B(n153), .Z(n148) ); AOI2